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On: July 6, 2023 Posted in Digital, Internet Comments: 0 Views: 114

Digital Logic Circuits (DLC) Solved MCQs

1.	Any signed negative binary number is recognised by its
A.	msb
B.	lsb
C.	byte
D.	nibble
Answer» A. msb

2.	The parameter through which 16 distinct values can be represented is known as
A.	bit
B.	byte
C.	word
D.	nibble
Answer» C. word

3.	The representation of octal number (532.2)8 in decimal is
A.	(346.25)10
B.	(532.864)10
C.	(340.67)10
D.	(531.668)10
Answer» A. (346.25)10

4.	The decimal equivalent of the binary number (1011.011)2 is
A.	(11.375)10
B.	(10.123)10
C.	(11.175)10
D.	(9.23)10
Answer» A. (11.375)10

5.	An important drawback of binary system is
A.	it requires very large string of 1’s and 0’s to represent a decimal number
B.	it requires sparingly small string of 1’s and 0’s to represent a decimal number
C.	it requires large string of 1’s and small string of 0’s to represent a decimal number
D.	it requires small string of 1’s and large string of 0’s to represent a decimal number
Answer» A. it requires very large string of 1’s and 0’s to represent a decimal number

6.	The decimal equivalent of the octal number (645)8 is
A.	(450)10
B.	(451)10
C.	(421)10
D.	(501)10
Answer» C. (421)10

7.	The largest two digit hexadecimal number is
A.	(fe)16
B.	(fd)16
C.	(ff)16
D.	(ef)16
Answer» C. (ff)16

8.	Representation of hexadecimal number (6DE)H in decimal:
A.	6 * 162 + 13 * 161 + 14 * 160
B.	6 * 162 + 12 * 161 + 13 * 160
C.	6 * 162 + 11 * 161 + 14 * 160
D.	6 * 162 + 14 * 161 + 15 * 160
Answer» A. 6 * 162 + 13 * 161 + 14 * 160

9.	The quantity of double word is
A.	16 bits
B.	32 bits
C.	4 bits
D.	8 bits
Answer» B. 32 bits

10.	What does RTL in digital circuit design stand for?
A.	register transfer language
B.	register transfer logic
C.	register transfer level
D.	resistor-transistor logic
Answer» C. register transfer level

11.	RTL is a design abstraction of what kind of circuit?
A.	asynchronous digital circuit
B.	synchronous digital circuit
C.	asynchronous sequential circuit
D.	analog circuit
Answer» B. synchronous digital circuit

12.	RTL is used in HDL to create what level of representations in the circuit?
A.	high-level
B.	low-level
C.	mid-level
D.	same level
Answer» A. high-level

13.	RTL mainly focuses on describing the flow of signals between
A.	logic gates
B.	registers
C.	clock
D.	inverter
Answer» B. registers

14.	Which flip-flop is usually used in the implementation of the registers?
A.	d flip-flop
B.	s-r flip-flop
C.	t flip-flop
D.	j-k flip-flop
Answer» A. d flip-flop

15.	Which of the following tool performs logic optimization?
A.	simulation tool
B.	synthesis tool
C.	routing tool
D.	rtl compiler
Answer» B. synthesis tool

16.	Hold time is the time needed for the data to after the edge of the clock is triggered.
A.	decrease
B.	increase
C.	remain constant
D.	negate
Answer» C. remain constant

17.	Simulator enters in which phase after the initialization phase?
A.	execution phase
B.	compilation phase
C.	elaboration phase
D.	simulation phase
Answer» A. execution phase

18.	All input of NOR as low produces result as
A.	low
B.	mid
C.	high
D.	floating
Answer» C. high

19.	In RTL NOR gate, the output is at logic 1 only when all the inputs are at
A.	logic 0
B.	logic 1
C.	+10v
D.	floating
Answer» A. logic 0

20.	The role of the is to convert the collector current into a voltage in RTL.
A.	collector resistor
B.	base resistor
C.	capacitor
D.	inductor
Answer» A. collector resistor

21.	The limitations of the one transistor RTL NOR gate are overcome by
A.	two-transistor rtl implementation
B.	three-transistor rtl implementation
C.	multi-transistor rtl implementation
D.	four-transistor rtl implementation
Answer» C. multi-transistor rtl implementation

22.	The primary advantage of RTL technology was that
A.	it results as low power dissipation
B.	it uses a minimum number of resistors
C.	it uses a minimum number of transistors
D.	it operates swiftly
Answer» C. it uses a minimum number of transistors

23.	The disadvantage of RTL is that
A.	it uses a maximum number of resistors
B.	it results in high power dissipation
C.	high noise creation
D.	it uses minimum number of transistors
Answer» B. it results in high power dissipation

24.	TTL circuits with “totem-pole” output stage minimize
A.	the power dissipation in rtl
B.	the time consumption in rtl
C.	the speed of transferring rate in rtl
D.	propagation delay in rtl
Answer» A. the power dissipation in rtl

26.	Diode–transistor logic (DTL) is the direct ancestor of
A.	register-transistor logic
B.	transistor–transistor logic
C.	high threshold logic
D.	emitter coupled logic
Answer» B. transistor–transistor logic

27.	In DTL logic gating function is performed by
A.	diode
B.	transistor
C.	inductor
D.	capacitor
Answer» A. diode

28.	In DTL amplifying function is performed by
A.	diode
B.	transistor
C.	inductor
D.	capacitor
Answer» B. transistor

29.	How many stages a DTL consist of?
A.	2
B.	3
C.	4
D.	5
Answer» B. 3

30.	The full form of CTDL is
A.	complemented transistor diode logic
B.	complemented transistor direct logic
C.	complementary transistor diode logic
D.	complementary transistor direct logic
Answer» A. complemented transistor diode logic

31.	The DTL propagation delay is relatively
A.	large
B.	small
C.	moderate
D.	negligible
Answer» A. large

32.	The way to speed up DTL is to add an across intermediate resister is
A.	small “speed-up” capacitor
B.	large “speed-up” capacitor
C.	small “speed-up” transistor
D.	large ” speed-up” transistor
Answer» A. small “speed-up” capacitor

33.	The process to avoid saturating the switching transistor is performed by
A.	baker clamp
B.	james r. biard
C.	chris brown
D.	totem-pole
Answer» A. baker clamp

34.	A major advantage of DTL over the earlier resistor–transistor logic is the
A.	increased fan out
B.	increased fan in
C.	decreased fan out
D.	decreased fan in
Answer» B. increased fan in

35.	To increase fan-out of the gate in DTL
A.	an additional capacitor may be used
B.	an additional resister may be used
C.	an additional transistor and diode may be used
D.	only an additional diode may be used
Answer» C. an additional transistor and diode may be used

36.	A disadvantage of DTL is
A.	the input transistor to the resister
B.	the input resister to the transistor
C.	the increased fan-in
D.	the increased fan-out
Answer» B. the input resister to the transistor

37.	Compatibility refers to
A.	the output of a circuit should match with the input of another circuit
B.	the output of a circuit should match with the input of the same circuit
C.	the input of a circuit should match with the output of another circuit
D.	the input of a circuit should match with the output of same circuit
Answer» A. the output of a circuit should match with the input of another circuit

38.	The method of connecting a driving device to a loading device is known as
A.	compatibility
B.	interface
C.	sourcing
D.	sinking
Answer» B. interface

39.	The first CML logic was introduced by General Electric in
A.	1960
B.	1981
C.	1961
D.	1990
Answer» C. 1961

40.	Schottky families prevent the saturating using
A.	transistors
B.	schottky transistors
C.	diodes
D.	schottky diodes
Answer» D. schottky diodes

41.	The basic idea of basic CML circuit came from an
A.	inverter
B.	buffer
C.	transistor
D.	both inverter and buffer
Answer» D. both inverter and buffer

42.	The full form of MECL is
A.	mono emitter coupled logic
B.	motorola emitter coupled logic
C.	motorola emitter capacitor logic
D.	both mono emitter and motorola coupled logic
Answer» B. motorola emitter coupled logic

43.	Motorola has offered MECL circuits in logic families.
A.	3
B.	4
C.	5
D.	6
Answer» C. 5

44.	The latest entrant to the ECL family is
A.	ecl 10k
B.	ecl 100k
C.	ecl 1000k
D.	ecl 10000k
Answer» B. ecl 100k

45.	All input of NOR as low produces result as
A.	low
B.	mid
C.	high
D.	high impedance
Answer» C. high

46.	In RTL NOR gate, the output is at logic 1 only when all the inputs are at
A.	logic 0
B.	logic 1
C.	+10v
D.	floating
Answer» A. logic 0

47.	The full form of CMOS is
A.	capacitive metal oxide semiconductor
B.	capacitive metallic oxide semiconductor
C.	complementary metal oxide semiconductor
D.	complemented metal oxide semiconductor
Answer» C. complementary metal oxide semiconductor

48.	The full form of COS-MOS is
A.	complementary symmetry metal oxide semiconductor
B.	complementary systematic metal oxide semiconductor
C.	capacitive symmetry metal oxide semiconductor
D.	complemented systematic metal oxide semiconductor
Answer» A. complementary symmetry metal oxide semiconductor

49.	CMOS is also sometimes referred to as
A.	capacitive metal oxide semiconductor
B.	capacitive symmetry metal oxide semiconductor
C.	complementary symmetry metal oxide semiconductor
D.	complemented symmetry metal oxide semiconductor
Answer» C. complementary symmetry metal oxide semiconductor

51.	Two important characteristics of CMOS devices are
A.	high noise immunity
B.	low static power consumption
C.	high resistivity
D.	both high noise immunity and low static power consumption
Answer» D. both high noise immunity and low static power consumption

52.	CMOS behaves as a/an
A.	adder
B.	subtractor
C.	inverter
D.	comparator
Answer» C. inverter

53.	An important characteristic of a CMOS circuit is the
A.	noise immunity
B.	duality
C.	symmetricity
D.	noise margin
Answer» B. duality

54.	CMOS logic dissipates power than NMOS logic circuits.
A.	more
B.	less
C.	equal
D.	very high
Answer» B. less

55.	Semiconductors are made of
A.	ge and si
B.	si and pb
C.	ge and pb
D.	pb and au
Answer» A. ge and si

56.	Which chip were the first RTC and CMOS RAM chip to be used in early IBM computers, capable of storing a total of 64 bytes?
A.	the samsung 146818
B.	the samsung 146819
C.	the motorola 146818
D.	the motorola 146819
Answer» C. the motorola 146818

57.	The full form of ECL is
A.	emitter-collector logic
B.	emitter-complementary logic
C.	emitter-coupled logic
D.	emitter-cored logic
Answer» C. emitter-coupled logic

58.	Which logic is the fastest of all the logic families?
A.	ttl
B.	ecl
C.	htl
D.	dtl
Answer» B. ecl

59.	Sometimes ECL can also be named as
A.	eel
B.	cel
C.	cml
D.	ccl
Answer» C. cml

60.	In an ECL the output is taken from
A.	emitter
B.	base
C.	collector
D.	junction of emitter and base
Answer» C. collector

61.	The ECL behaves as
A.	not gate
B.	nor gate
C.	nand gate
D.	and gate
Answer» B. nor gate

62.	In ECL the fanout capability is
A.	high
B.	low
C.	zero
D.	sometimes high and sometimes low
Answer» A. high

63.	ECL’s major disadvantage is that
A.	it requires more power
B.	it’s fanout capability is high
C.	it creates more noise
D.	it is slow
Answer» A. it requires more power

64.	The full form of SCFL is
A.	source-collector logic
B.	source-coupled logic
C.	source-complementary logic
D.	source cored logic
Answer» B. source-coupled logic

65.	The equivalent of emitter-coupled logic made out of FETs is called
A.	cml
B.	scfl
C.	fecl
D.	efcl
Answer» B. scfl

66.	ECL was invented in by
A.	1956, baker clamp
B.	1976, james r. biard
C.	1956, hannon s. yourke
D.	1976, yourke
Answer» C. 1956, hannon s. yourke

67.	At the time of invention, an ECL was called as
A.	source-coupled logic
B.	current mode logic
C.	current-steering logic
D.	emitter-coupled logic
Answer» C. current-steering logic

68.	The ECL circuits usually operates with
A.	negative voltage
B.	positive voltage
C.	grounded voltage
D.	high voltage
Answer» A. negative voltage

69.	Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of
A.	ecl
B.	vecl
C.	pecl
D.	lecl
Answer» C. pecl

70.	Transistor–transistor logic (TTL) is a class of digital circuits built from
A.	jfet only
B.	bipolar junction transistors (bjt)
C.	resistors
D.	bipolar junction transistors (bjt) and resistors
Answer» D. bipolar junction transistors (bjt) and resistors

71.	TTL was invented in 1961 by
A.	baker clamp
B.	james l. buie
C.	chris brown
D.	frank wanlass
Answer» B. james l. buie

72.	The full form of TCTL is
A.	transistor-coupled transistor logic
B.	transistor-capacitor transistor logic
C.	transistor-complemented transistor logic
D.	transistor-complementary transistor logic
Answer» A. transistor-coupled transistor logic

73.	The ancestor to the first personal computers.
A.	param 1
B.	satyam 1
C.	kenbak 1
D.	mits altair
Answer» C. kenbak 1

74.	TTL inputs are the emitters of a
A.	transistor-transistor logic
B.	multiple-emitter transistor
C.	resistor-transistor logic
D.	diode-transistor logic
Answer» B. multiple-emitter transistor

76.	Standard TTL circuits operate with a volt power supply.
A.	2
B.	4
C.	5
D.	3
Answer» C. 5

77.	A TTL gate may operate inadvertently as an
A.	digital amplifier
B.	analog amplifier
C.	inverter
D.	regulator
Answer» B. analog amplifier

78.	Which statement below best describes a Karnaugh map?
A.	it is simply a rearranged truth table
B.	the karnaugh map eliminates the need for using nand and nor gates
C.	variable complements can be eliminated by using karnaugh maps
D.	a karnaugh map can be used to replace boolean rules
Answer» A. it is simply a rearranged truth table

79.	Which of the examples below expresses the commutative law of multiplication?
A.	a + b = b + a
B.	a • b = b + a
C.	a • (b • c) = (a • b) • c
D.	a • b = b • a
Answer» D. a • b = b • a

80.	The Boolean expression Y = (AB)’ is logically equivalent to what single gate?
A.	nand
B.	nor
C.	and
D.	or
Answer» A. nand

81.	The systematic reduction of logic circuits is accomplished by:
A.	symbolic reduction
B.	ttl logic
C.	using boolean algebra
D.	using a truth table
Answer» C. using boolean algebra

82.	Each “1” entry in a K-map square represents:
A.	a high for each input truth table condition that produces a high output
B.	a high output on the truth table for all low input combinations
C.	a low output for all possible high input conditions
D.	a don’t care condition for all possible input truth table combinations
Answer» A. a high for each input truth table condition that produces a high output

83.	Each “0” entry in a K-map square represents:
A.	a high for each input truth table condition that produces a high output
B.	a high output on the truth table for all low input combinations
C.	a low output for all possible high input conditions
D.	a don’t care condition for all possible input truth table combinations
Answer» A. a high for each input truth table condition that produces a high output

84.	Looping on a K-map always results in the elimination of
A.	variables within the loop that appear only in their complemented form
B.	variables that remain unchanged within the loop
C.	variables within the loop that appear in both complemented and uncomplemented form
D.	variables within the loop that appear only in their uncomplemented form
Answer» C. variables within the loop that appear in both complemented and uncomplemented form

85.	Which of the following expressions is in the sum-of-products form?
A.	(a + b)(c + d)
B.	(a * b)(c * d)
C.	a* b *(cd)
D.	a * b + c * d
Answer» D. a * b + c * d

86.	What is an ambiguous condition in a NAND based S’-R’ latch?
A.	s’=0, r’=1
B.	s’=1, r’=0
C.	s’=1, r’=1
D.	s’=0, r’=0
Answer» D. s’=0, r’=0

87.	In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is
A.	no change
B.	set
C.	reset
D.	forbidden
Answer» A. no change

88.	A NAND based S’-R’ latch can be converted into S-R latch by placing
A.	a d latch at each of its input
B.	an inverter at each of its input
C.	it can never be converted
D.	both a d latch and an inverter at its input
Answer» D. both a d latch and an inverter at its input

89.	The difference between a flip-flop & latch is
A.	both are same
B.	flip-flop consist of an extra output
C.	latches has one input but flip-flop has two
D.	latch has two inputs but flip-flop has one
Answer» C. latches has one input but flip-flop has two

90.	How many types of flip-flops are?
A.	2
B.	3
C.	4
D.	5
Answer» C. 4

91.	The S-R flip flop consist of
A.	4 and gates
B.	two additional and gates
C.	an additional clock input
D.	3 and gates
Answer» B. two additional and gates

92.	What is one disadvantage of an S-R flip-flop?
A.	it has no enable input
B.	it has a race condition
C.	it has no clock input
D.	invalid state
Answer» D. invalid state

93.	One example of the use of an S-R flip-flop is as
A.	racer
B.	stable oscillator
C.	binary storage register
D.	transition pulse generator
Answer» C. binary storage register

94.	When is a flip-flop said to be transparent?
A.	when the q output is opposite the input
B.	when the q output follows the input
C.	when you can see through the ic packaging
D.	when the q output is complementary of the input
Answer» B. when the q output follows the input

95.	On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
A.	the clock pulse is low
B.	the clock pulse is high
C.	the clock pulse transitions from low to high
D.	the clock pulse transitions from high to low
Answer» C. the clock pulse transitions from low to high

96.	What is the hold condition of a flip-flop?
A.	both s and r inputs activated
B.	no active s or r input
C.	only s is active
D.	only r is active
Answer» B. no active s or r input

97.	One example of the use of an S-R flip-flop is as
A.	transition pulse generator
B.	racer
C.	switch debouncer
D.	astable oscillator
Answer» C. switch debouncer

98.	The truth table for an S-R flip-flop has how many VALID entries?
A.	1
B.	2
C.	3
D.	4
Answer» C. 3

99.	When both inputs of a J-K flip-flop cycle, the output will
A.	be invalid
B.	change
C.	not change
D.	toggle
Answer» C. not change

101.	A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
A.	and or or gates
B.	xor or xnor gates
C.	nor or nand gates
D.	and or nor gates
Answer» C. nor or nand gates

102.	The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
A.	combinational circuits
B.	sequential circuits
C.	latches
D.	flip-flops
Answer» B. sequential circuits

103.	Whose operations are more faster among the following?
A.	combinational circuits
B.	sequential circuits
C.	latches
D.	flip-flops
Answer» A. combinational circuits

104.	How many types of sequential circuits are?
A.	2
B.	3
C.	4
D.	5
Answer» A. 2

105.	The sequential circuit is also called
A.	flip-flop
B.	latch
C.	strobe
D.	adder
Answer» B. latch

106.	The basic latch consists of
A.	two inverters
B.	two comparators
C.	two amplifiers
D.	two adders
Answer» A. two inverters

107.	In S-R flip-flop, if Q = 0 the output is said to be
A.	set
B.	reset
C.	previous state
D.	current state
Answer» B. reset

108.	The output of latches will remain in set/reset untill
A.	the trigger pulse is given to change the state
B.	any pulse given to go into previous state
C.	they don’t get any pulse more
D.	the pulse is edge-triggered
Answer» A. the trigger pulse is given to change the state

109.	What is a trigger pulse?
A.	a pulse that starts a cycle of operation
B.	a pulse that reverses the cycle of operation
C.	a pulse that prevents a cycle of operation
D.	a pulse that enhances a cycle of operation
Answer» A. a pulse that starts a cycle of operation

110.	A latch is an example of a
A.	monostable multivibrator
B.	astable multivibrator
C.	bistable multivibrator
D.	555 timer
Answer» C. bistable multivibrator

111.	Latch is a device with
A.	one stable state
B.	two stable state
C.	three stable state
D.	infinite stable states
Answer» B. two stable state

112.	Why latches are called a memory devices?
A.	it has capability to stare 8 bits of data
B.	it has internal memory of 4 bit
C.	it can store one bit of data
D.	it can store infinite amount of data
Answer» C. it can store one bit of data

113.	Two stable states of latches are
A.	astable & monostable
B.	low input & high output
C.	high output & low output
D.	low output & high input
Answer» C. high output & low output

114.	How many types of latches are __
A.	4
B.	3
C.	2
D.	5
Answer» A. 4

115.	The full form of SR is
A.	system rated
B.	set reset
C.	set ready
D.	set rated
Answer» B. set reset

116.	The SR latch consists of
A.	1 input
B.	2 inputs
C.	3 inputs
D.	4 inputs
Answer» B. 2 inputs

117.	The outputs of SR latch are
A.	x and y
B.	a and b
C.	s and r
D.	q and q’
Answer» D. q and q’

118.	The first step of analysis procedure of SR latch is to
A.	label inputs
B.	label outputs
C.	label states
D.	label tables
Answer» B. label outputs

119.	The inputs of SR latch are
A.	x and y
B.	a and b
C.	s and r
D.	j and k
Answer» C. s and r

120.	When a high is applied to the Set line of an SR latch, then
A.	q output goes high
B.	q’ output goes high
C.	q output goes low
D.	both q and q’ go high
Answer» A. q output goes high

121.	When both inputs of SR latches are low, the latch
A.	q output goes high
B.	q’ output goes high
C.	it remains in its previously set or reset state
D.	it goes to its next set or reset state
Answer» C. it remains in its previously set or reset state

122.	When both inputs of SR latches are high, the latch goes
A.	unstable
B.	stable
C.	metastable
D.	bistable
Answer» C. metastable

123.	The full form of MOS is
A.	metal oxide semiconductor
B.	metal oxygen semiconductor
C.	metallic oxide semiconductor
D.	metallic oxygen semiconductor
Answer» A. metal oxide semiconductor

124.	What are the types of MOSFET devices available?
A.	p-type enhancement type mosfet
B.	n-type enhancement type mosfet
C.	depletion type mosfet
D.	all of the mentioned
Answer» D. all of the mentioned

126.	A technique used to reduce the magnitude of threshold voltage of MOSFET is the
A.	use of complementary mosfet
B.	use of silicon nitride
C.	using thin film technology
D.	increasing potential of the channel
Answer» B. use of silicon nitride

127.	What is used to higher the speed of operation in MOSFET fabrication?
A.	ceramic gate
B.	silicon dioxide
C.	silicon nitride
D.	poly silicon gate
Answer» D. poly silicon gate

128.	Why MOSFET is preferred over BJT in IC components?
A.	mosfet has low packing density
B.	mosfet has medium packing density
C.	mosfet has high packing density
D.	mosfet has no packing density
Answer» A. mosfet has low packing density

129.	Critical defects per unit chip area is for a MOS transistor.
A.	high
B.	low
C.	neutral
D.	very high
Answer» B. low

130.	MOS is being used in
A.	lsi
B.	vlsi
C.	msi
D.	both lsi and vlsi
Answer» D. both lsi and vlsi

131.	The D flip-flop has input.
A.	1
B.	2
C.	3
D.	4
Answer» A. 1

132.	The D flip-flop has output/outputs.
A.	2
B.	3
C.	4
D.	1
Answer» A. 2

133.	A D flip-flop can be constructed from an _ flip-flop.
A.	s-r
B.	j-k
C.	t
D.	s-k
Answer» A. s-r

134.	In D flip-flop, if clock input is HIGH & D=1, then output is
A.	0
B.	1
C.	forbidden
D.	toggle
Answer» A. 0

135.	Which of the following is correct for a gated D flip-flop?
A.	the output toggles if one of the inputs is held high
B.	only one of the inputs can be high at a time
C.	the output complement follows the input when enabled
D.	q output follows the input d when the enable is high
Answer» D. q output follows the input d when the enable is high

136.	With regard to a D latch
A.	the q output follows the d input when en is low
B.	the q output is opposite the d input when en is low
C.	the q output follows the d input when en is high
D.	the q output is high regardless of en’s input state
Answer» C. the q output follows the d input when en is high

137.	Which of the following is correct for a D latch?
A.	the output toggles if one of the inputs is held high
B.	q output follows the input d when the enable is high
C.	only one of the inputs can be high at a time
D.	the output complement follows the input when enabled
Answer» B. q output follows the input d when the enable is high

138.	Which of the following describes the operation of a positive edge-triggered D flip-flop?
A.	if both inputs are high, the output will toggle
B.	the output will follow the input on the leading edge of the clock
C.	when both inputs are low, an invalid state exists
D.	the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
Answer» B. the output will follow the input on the leading edge of the clock

139.	A positive edge-triggered D flip-flop will store a 1 when
A.	the d input is high and the clock transitions from high to low
B.	the d input is high and the clock transitions from low to high
C.	the d input is high and the clock is low
D.	the d input is high and the clock is high
Answer» B. the d input is high and the clock transitions from low to high

140.	Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
A.	due to its capability to receive data from flip-flop
B.	due to its capability to store data in flip-flop
C.	due to its capability to transfer the data into flip-flop
D.	due to erasing the data from the flip-flop
Answer» C. due to its capability to transfer the data into flip-flop

141.	The characteristic equation of D-flip-flop implies that
A.	the next state is dependent on previous state
B.	the next state is dependent on present state
C.	the next state is independent of previous state
D.	the next state is independent of present state
Answer» D. the next state is independent of present state

142.	The asynchronous input can be used to set the flip-flop to the
A.	1 state
B.	0 state
C.	either 1 or 0 state
D.	forbidden state
Answer» C. either 1 or 0 state

143.	Input clock of RS flip-flop is given to
A.	input
B.	pulser
C.	output
D.	master slave flip-flop
Answer» B. pulser

144.	D flip-flop is a circuit having
A.	2 nand gates
B.	3 nand gates
C.	4 nand gates
D.	5 nand gates
Answer» C. 4 nand gates

145.	At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?
A.	conversion condition
B.	race around condition
C.	lock out state
D.	forbidden state
Answer» B. race around condition

146.	Master slave flip flop is also referred to as?
A.	level triggered flip flop
B.	pulse triggered flip flop
C.	edge triggered flip flop
D.	edge-level triggered flip flop
Answer» B. pulse triggered flip flop

147.	In a positive edge triggered JK flip flop, a low J and low K produces?
A.	high state
B.	low state
C.	toggle state
D.	no change state
Answer» D. no change state

148.	If one wants to design a binary counter, the preferred type of flip-flop is
A.	d type
B.	s-r type
C.	latch
D.	j-k type
Answer» D. j-k type

149.	S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
A.	or gate
B.	and gate
C.	inverter
D.	full adder
Answer» C. inverter

151.	Which of the following is the Universal Flip-flop?
A.	s-r flip-flop
B.	j-k flip-flop
C.	master slave flip-flop
D.	d flip-flop
Answer» B. j-k flip-flop

152.	How many types of triggering takes place in a flip flops?
A.	3
B.	2
C.	4
D.	5
Answer» A. 3

153.	The term synchronous means _
A.	the output changes state only when any of the input is triggered
B.	the output changes state only when the clock input is triggered
C.	the output changes state only when the input is reversed
D.	the output changes state only when the input follows it
Answer» B. the output changes state only when the clock input is triggered

154.	The S-R, J-K and D inputs are called
A.	asynchronous inputs
B.	synchronous inputs
C.	bidirectional inputs
D.	unidirectional inputs
Answer» B. synchronous inputs

155.	The characteristic of J-K flip-flop is similar to
A.	s-r flip-flop
B.	d flip-flop
C.	t flip-flop
D.	gated t flip-flop
Answer» A. s-r flip-flop

156.	A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting
A.	two and gates
B.	two nand gates
C.	two not gates
D.	two or gates
Answer» A. two and gates

157.	What is the significance of the J and K terminals on the J-K flip-flop?
A.	there is no known significance in their designations
B.	the j represents “jump,” which is how the q output reacts whenever the clock goes high and the j input is also high
C.	the letters were chosen in honour of jack kilby, the inventory of the integrated circuit
D.	all of the other letters of the alphabet are already in use
Answer» C. the letters were chosen in honour of jack kilby, the inventory of the integrated circuit

158.	48 MHz.
A.	10.24 khz
B.	5 khz
C.	30.24 khz
D.	15 khz
Answer» B. 5 khz

159.	How many flip-flops are in the 7475 IC?
A.	2
B.	1
C.	4
D.	8
Answer» C. 4

160.	In parts of the processor, adders are used to calculate
A.	addresses
B.	table indices
C.	increment and decrement operators
D.	all of the mentioned
Answer» D. all of the mentioned

161.	Total number of inputs in a half adder is
A.	2
B.	3
C.	4
D.	1
Answer» A. 2

162.	In which operation carry is obtained?
A.	subtraction
B.	addition
C.	multiplication
D.	both addition and subtraction
Answer» B. addition

163.	If A and B are the inputs of a half adder, the sum is given by
A.	a and b
B.	a or b
C.	a xor b
D.	a ex-nor b
Answer» C. a xor b

164.	If A and B are the inputs of a half adder, the carry is given by
A.	a and b
B.	a or b
C.	a xor b
D.	a ex-nor b
Answer» A. a and b

165.	Half-adders have a major limitation in that they cannot
A.	accept a carry bit from a present stage
B.	accept a carry bit from a next stage
C.	accept a carry bit from a previous stage
D.	accept a carry bit from the following stages
Answer» C. accept a carry bit from a previous stage

166.	The difference between half adder and full adder is
A.	half adder has two inputs while full adder has four inputs
B.	half adder has one output while full adder has two outputs
C.	half adder has two inputs while full adder has three inputs
D.	all of the mentioned
Answer» C. half adder has two inputs while full adder has three inputs

167.	If A, B and C are the inputs of a full adder then the sum is given by
A.	a and b and c
B.	a or b and c
C.	a xor b xor c
D.	a or b or c
Answer» C. a xor b xor c

168.	If A, B and C are the inputs of a full adder then the carry is given by
A.	a and b or (a or b) and c
B.	a or b or (a and b) c
C.	(a and b) or (a and b)c
D.	a xor b xor (a xor b) and c
Answer» A. a and b or (a or b) and c

169.	Half subtractor is used to perform subtraction of
A.	2 bits
B.	3 bits
C.	4 bits
D.	5 bits
Answer» A. 2 bits

170.	For subtracting 1 from 0, we use to take a from neighbouring bits.
A.	carry
B.	borrow
C.	input
D.	output
Answer» B. borrow

171.	How many outputs are required for the implementation of a subtractor?
A.	1
B.	2
C.	3
D.	4
Answer» B. 2

172.	Let the input of a subtractor is A and B then what the output will be if A = B?
A.	0
B.	1
C.	a
D.	b
Answer» A. 0

173.	Let A and B is the input of a subtractor then the output will be
A.	a xor b
B.	a and b
C.	a or b
D.	a exnor b
Answer» A. a xor b

174.	Let A and B is the input of a subtractor then the borrow will be
A.	a and b’
B.	a’ and b
C.	a or b
D.	a and b
Answer» B. a’ and b

176.	Full subtractor is used to perform subtraction of
A.	2 bits
B.	3 bits
C.	4 bits
D.	8 bits
Answer» B. 3 bits

177.	The full subtractor can be implemented using
A.	two xor and an or gates
B.	two half subtractors and an or gate
C.	two multiplexers and an and gate
D.	two comparators and an and gate
Answer» B. two half subtractors and an or gate

178.	The output of a subtractor is given by (if A, B and X are the inputs).
A.	a and b xor x
B.	a xor b xor x
C.	a or b nor x
D.	a nor b xor x
Answer» B. a xor b xor x

179.	The output of a full subtractor is same as
A.	half adder
B.	full adder
C.	half subtractor
D.	decoder
Answer» B. full adder

180.	A register is defined as
A.	the group of latches for storing one bit of information
B.	the group of latches for storing n-bit of information
C.	the group of flip-flops suitable for storing one bit of information
D.	the group of flip-flops suitable for storing binary information
Answer» D. the group of flip-flops suitable for storing binary information

181.	The register is a type of
A.	sequential circuit
B.	combinational circuit
C.	cpu
D.	latches
Answer» A. sequential circuit

182.	How many types of registers are?
A.	2
B.	3
C.	4
D.	5
Answer» C. 4

183.	The main difference between a register and a counter is
A.	a register has no specific sequence of states
B.	a counter has no specific sequence of states
C.	a register has capability to store one bit of information but counter has n-bit
D.	a register counts data
Answer» A. a register has no specific sequence of states

184.	In D register, ‘D’ stands for
A.	delay
B.	decrement
C.	data
D.	decay
Answer» C. data

185.	Registers capable of shifting in one direction is
A.	universal shift register
B.	unidirectional shift register
C.	unipolar shift register
D.	unique shift register
Answer» B. unidirectional shift register

186.	A register that is used to store binary information is called
A.	data register
B.	binary register
C.	shift register
D.	d – register
Answer» B. binary register

187.	A shift register is defined as
A.	the register capable of shifting information to another register
B.	the register capable of shifting information either to the right or to the left
C.	the register capable of shifting information to the right only
D.	the register capable of shifting information to the left only
Answer» B. the register capable of shifting information either to the right or to the left

188.	How many methods of shifting of data are available?
A.	2
B.	3
C.	4
D.	5
Answer» A. 2

189.	In serial shifting method, data shifting occurs
A.	one bit at a time
B.	simultaneously
C.	two bit at a time
D.	four bit at a time
Answer» A. one bit at a time

190.	What is a recirculating register?
A.	serial out connected to serial in
B.	all q outputs connected together
C.	a register that can be used over again
D.	parallel out connected to parallel in
Answer» A. serial out connected to serial in

191.	When is it important to use a three-state buffer?
A.	when two or more outputs are connected to the same input
B.	when all outputs are normally high
C.	when all outputs are normally low
D.	when two or more outputs are connected to two or more inputs
Answer» A. when two or more outputs are connected to the same input

192.	After two clock pulses, the register contains
A.	10111000
B.	10110111
C.	11110000
D.	11111100
Answer» D. 11111100

193.	How much storage capacity does each stage in a shift register represent?
A.	one bit
B.	two bits
C.	four bits
D.	eight bits
Answer» A. one bit

194.	The decimal number system represents the decimal number in the form of
A.	hexadecimal
B.	binary coded
C.	octal
D.	decimal
Answer» B. binary coded

195.	29 input circuit will have total of
A.	32 entries
B.	128 entries
C.	256 entries
D.	512 entries
Answer» D. 512 entries

196.	BCD adder can be constructed with 3 IC packages each of
A.	2 bits
B.	3 bits
C.	4 bits
D.	5 bits
Answer» C. 4 bits

197.	The output sum of two decimal digits can be represented in
A.	gray code
B.	excess-3
C.	bcd
D.	hexadecimal
Answer» C. bcd

198.	The addition of two decimal digits in BCD can be done through
A.	bcd adder
B.	full adder
C.	ripple carry adder
D.	carry look ahead
Answer» A. bcd adder

199.	3 bits full adder contains
A.	3 combinational inputs
B.	4 combinational inputs
C.	6 combinational inputs
D.	8 combinational inputs
Answer» D. 8 combinational inputs

201.	Complement of F’ gives back
A.	f’
B.	f
C.	ff
D.	ff’
Answer» B. f

202.	Decimal digit in BCD can be represented by
A.	1 input line
B.	2 input lines
C.	3 input lines
D.	4 input lines
Answer» D. 4 input lines

203.	The number of logic gates and the way of their interconnections can be classified as
A.	logical network
B.	system network
C.	circuit network
D.	gate network
Answer» A. logical network

204.	EPROM uses an array of
A.	p-channel enhancement type mosfet
B.	n-channel enhancement type mosfet
C.	p-channel depletion type mosfet
D.	n-channel depletion type mosfet
Answer» B. n-channel enhancement type mosfet

205.	The EPROM was invented by
A.	wen tsing chow
B.	dov frohman
C.	luis o brian
D.	j p longwell
Answer» B. dov frohman

206.	Address decoding for dynamic memory chip control may also be used for
A.	chip selection and address location
B.	read and write control
C.	controlling refresh circuits
D.	memory mapping
Answer» A. chip selection and address location

207.	Which of the following describes the action of storing a bit of data in a mask ROM?
A.	a 0 is stored by connecting the gate of a mos cell to the address line
B.	a 0 is stored in a bipolar cell by shorting the base connection to the address line
C.	a 1 is stored by connecting the gate of a mos cell to the address line
D.	a 1 is stored in a bipolar cell by opening the base connection to the address line
Answer» C. a 1 is stored by connecting the gate of a mos cell to the address line

208.	The check sum method of testing a ROM
A.	allows data errors to be pinpointed to a specific memory location
B.	provides a means for locating and correcting data errors in specific memory locations
C.	indicates if the data in more than one memory location is incorrect
D.	simply indicates that the contents of the rom are incorrect
Answer» D. simply indicates that the contents of the rom are incorrect

209.	The initial values in all the cells of an EPROM is
A.	0
B.	1
C.	both 0 and 1
D.	alternate 0s and 1s
Answer» B. 1

210.	To store 0 in such a cell, the floating point must be
A.	reprogrammed
B.	restarted
C.	charged
D.	power off
Answer» C. charged

211.	The major disadvantage of RAM is?
A.	its access speed is too slow
B.	its matrix size is too big
C.	it is volatile
D.	high power consumption
Answer» C. it is volatile

212.	Which one of the following is used for the fabrication of MOS EPROM?
A.	tms 2513
B.	tms 2515
C.	tms 2516
D.	tms 2518
Answer» C. tms 2516

213.	How many addresses a MOS EPROM have?
A.	1024
B.	512
C.	2516
D.	256
Answer» C. 2516

214.	ROMs retain data when
A.	power is on
B.	power is off
C.	system is down
D.	all of the mentioned
Answer» D. all of the mentioned

215.	When a RAM module passes the checker board test it is
A.	able to read and write only 0s
B.	faulty
C.	probably good
D.	able to read and write only 1s
Answer» C. probably good

216.	What is the difference between static RAM and dynamic RAM?
A.	static ram must be refreshed, dynamic ram does not
B.	there is no difference
C.	dynamic ram must be refreshed, static ram does not
D.	sram is slower than dram
Answer» C. dynamic ram must be refreshed, static ram does not

217.	How many natural states will there be in a 4-bit ripple counter?
A.	4
B.	8
C.	16
D.	32
Answer» C. 16

218.	A ripple counter’s speed is limited by the propagation delay of
A.	each flip-flop
B.	all flip-flops and gates
C.	the flip-flops only with gates
D.	only circuit gates
Answer» A. each flip-flop

219.	One of the major drawbacks to the use of asynchronous counters is that
A.	low-frequency applications are limited because of internal propagation delays
B.	high-frequency applications are limited because of internal propagation delays
C.	asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
D.	asynchronous counters do not have propagation delays, which limits their use in high- frequency applications
Answer» B. high-frequency applications are limited because of internal propagation delays

220.	Internal propagation delay of asynchronous counter is removed by
A.	ripple counter
B.	ring counter
C.	modulus counter
D.	synchronous counter
Answer» D. synchronous counter

221.	How many flip-flops are required to construct a decade counter?
A.	4
B.	8
C.	5
D.	10
Answer» A. 4

222.	The terminal count of a typical modulus-10 binary counter is
A.	0000
B.	1010
C.	1001
D.	1111
Answer» C. 1001

223.	A ripple counter’s speed is limited by the propagation delay of
A.	each flip-flop
B.	all flip-flops and gates
C.	the flip-flops only with gates
D.	only circuit gates
Answer» A. each flip-flop

224.	A 4-bit counter has a maximum modulus of
A.	3
B.	6
C.	8
D.	16
Answer» D. 16

226.	UP-DOWN counter is also known as
A.	dual counter
B.	multi counter
C.	multimode counter
D.	two counter
Answer» C. multimode counter

227.	In an UP-counter, each flip-flop is triggered by
A.	the output of the next flip-flop
B.	the normal output of the preceding flip-flop
C.	the clock pulse of the previous flip-flop
D.	the inverted output of the preceding flip-flop
Answer» B. the normal output of the preceding flip-flop

228.	In DOWN-counter, each flip-flop is triggered by
A.	the output of the next flip-flop
B.	the normal output of the preceding flip-flop
C.	the clock pulse of the previous flip-flop
D.	the inverted output of the preceding flip-flop
Answer» D. the inverted output of the preceding flip-flop

229.	Binary counter that count incrementally and decrement is called
A.	up-down counter
B.	lsi counters
C.	down counter
D.	up counter
Answer» A. up-down counter

230.	Once an up-/down-counter begins its count sequence, it
A.	starts counting
B.	can be reversed
C.	can’t be reversed
D.	can be altered
Answer» D. can be altered

231.	In 4-bit up-down counter, how many flip-flops are required?
A.	2
B.	3
C.	4
D.	5
Answer» C. 4

232.	A modulus-10 counter must have _
A.	10 flip-flops
B.	4 flip-flops
C.	2 flip-flops
D.	synchronous clocking
Answer» B. 4 flip-flops

233.	Which is not an example of a truncated modulus?
A.	8
B.	9
C.	11
D.	15
Answer» A. 8

234.	The designation means that the
A.	up count is active-high, the down count is active-low
B.	up count is active-low, the down count is active-high
C.	up and down counts are both active-low
D.	up and down counts are both active-high
Answer» A. up count is active-high, the down count is active-low

235.	The full form of SIPO is
A.	serial-in parallel-out
B.	parallel-in serial-out
C.	serial-in serial-out
D.	serial-in peripheral-out
Answer» A. serial-in parallel-out

236.	How can parallel data be taken out of a shift register simultaneously?
A.	use the q output of the first ff
B.	use the q output of the last ff
C.	tie all of the q outputs together
D.	use the q output of each ff
Answer» D. use the q output of each ff

237.	What is meant by parallel load of a shift register?
A.	all ffs are preset with data
B.	each ff is loaded with data, one at a time
C.	parallel shifting of data
D.	all ffs are set with data
Answer» A. all ffs are preset with data

238.	After three clock pulses, the register contains
A.	01110
B.	00001
C.	00101
D.	00110
Answer» C. 00101

239.	What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
A.	1100
B.	0011
C.	0000
D.	1111
Answer» C. 0000

240.	In digital logic, a counter is a device which
A.	counts the number of outputs
B.	stores the number of times a particular event or process has occurred
C.	stores the number of times a clock pulse rises and falls
D.	counts the number of inputs
Answer» B. stores the number of times a particular event or process has occurred

241.	A counter circuit is usually constructed of
A.	a number of latches connected in cascade form
B.	a number of nand gates connected in cascade form
C.	a number of flip-flops connected in cascade
D.	a number of nor gates connected in cascade form
Answer» C. a number of flip-flops connected in cascade

242.	How many types of the counter are there?
A.	2
B.	3
C.	4
D.	5
Answer» B. 3

243.	A decimal counter has states.
A.	5
B.	10
C.	15
D.	20
Answer» B. 10

244.	Ripple counters are also called
A.	ssi counters
B.	asynchronous counters
C.	synchronous counters
D.	vlsi counters
Answer» B. asynchronous counters

245.	Synchronous counter is a type of
A.	ssi counters
B.	lsi counters
C.	msi counters
D.	vlsi counters
Answer» C. msi counters

246.	Three decade counter would have
A.	2 bcd counters
B.	3 bcd counters
C.	4 bcd counters
D.	5 bcd counters
Answer» B. 3 bcd counters

247.	BCD counter is also known as
A.	parallel counter
B.	decade counter
C.	synchronous counter
D.	vlsi counter
Answer» B. decade counter

248.	The parallel outputs of a counter circuit represent the
A.	parallel data word
B.	clock frequency
C.	counter modulus
D.	clock count
Answer» D. clock count

249.	The time from the beginning of a read cycle to the end of tACS/tAA is called as
A.	write enable time
B.	data hold
C.	read cycle time
D.	access time
Answer» D. access time

251.	Which of the following is programmed electrically by the user?
A.	rom
B.	eprom
C.	prom
D.	eeprom
Answer» C. prom

252.	PROMs are available in
A.	bipolar and mosfet technologies
B.	mosfet and fet technologies
C.	fet and bipolar technologies
D.	mos and bipolar technologies
Answer» D. mos and bipolar technologies

253.	Which of the following best describes the fusible-link PROM?
A.	manufacturer-programmable, reprogrammable
B.	manufacturer-programmable, one-time programmable
C.	user-programmable, reprogrammable
D.	user-programmable, one-time programmable
Answer» D. user-programmable, one-time programmable

254.	How can ultraviolet erasable PROMs be recognized?
A.	there is a small window on the chip
B.	they will have a small violet dot next to the #1 pin
C.	their part number always starts with a “u”, such as in u12
D.	they are not readily identifiable, since they must always be kept under a small cover
Answer» A. there is a small window on the chip

255.	Which part of a Flash memory architecture manages all chip functions?
A.	program verify code
B.	floating-gate mosfet
C.	command code
D.	input/output pins
Answer» B. floating-gate mosfet

256.	How much locations an 8-bit address code can select in memory?
A.	8 locations
B.	256 locations
C.	65,536 locations
D.	131,072 locations
Answer» B. 256 locations

257.	What is a fusing process?
A.	it is a process by which data is passed to the memory
B.	it is a process by which data is read through the memory
C.	it is a process by which programs are burnout to the diode/transistors
D.	it is a process by which data is fetched through the memory
Answer» C. it is a process by which programs are burnout to the diode/transistors

258.	Fusing process is
A.	reversible
B.	irreversible
C.	synchronous
D.	asynchronous
Answer» B. irreversible

259.	The cell type used inside a PROM is
A.	link cells
B.	metal cells
C.	fuse cells
D.	electric cells
Answer» C. fuse cells

260.	How many types of fuse technologies are used in PROMs?
A.	2
B.	3
C.	4
D.	5
Answer» B. 3

261.	Metal links are made up of
A.	polycrystalline
B.	magnesium sulphide
C.	nichrome
D.	silicon dioxide
Answer» C. nichrome

262.	Silicon links are made up of
A.	polycrystalline silicon
B.	polycrystalline magnesium
C.	nichrome
D.	silicon dioxide
Answer» A. polycrystalline silicon

263.	During programming p-n junction is
A.	avalanche reverse biased
B.	avalanche forward biased
C.	zener reverse biased
D.	zener reverse biased
Answer» A. avalanche reverse biased

264.	The full form of FAMOS is
A.	floating gate avalanche injection mos
B.	float gate avalanche injection mos
C.	floating gate avalanche induction mos
D.	float gate avalanche induction mos
Answer» A. floating gate avalanche injection mos

265.	PROM is programmed by
A.	eprom programmer
B.	eeprom programmer
C.	prom programmer
D.	rom programmer
Answer» C. prom programmer

266.	The PROM starts out with
A.	1s
B.	0s
C.	null
D.	both 1s and 0s
Answer» B. 0s

267.	For implementation of PROM, which IC is used?
A.	ic 74187
B.	ic 74186
C.	ic 74185
D.	ic 74184
Answer» B. ic 74186

268.	IC 74186 is of
A.	1024 bits
B.	32 bits
C.	512 bits
D.	64 bits
Answer» C. 512 bits

269.	How many memory locations are addressed using 18 address bits?
A.	165,667
B.	245,784
C.	262,144
D.	212,342
Answer» C. 262,144

270.	*How many address bits are needed to operate a 2K 8-bit memory?**
A.	10
B.	11
C.	12
D.	13
Answer» B. 11

271.	What is the bit storage capacity of a ROM with a 1024 × 8 organization?
A.	1024
B.	4096
C.	2048
D.	8192
Answer» D. 8192

272.	The logical sum of two or more logical product terms is called
A.	sop
B.	pos
C.	or operation
D.	nand operation
Answer» A. sop

273.	The expression Y=AB+BC+AC shows the operation.
A.	ex-or
B.	sop
C.	pos
D.	nor
Answer» B. sop

274.	The expression Y=(A+B)(B+C)(C+A) shows the operation.
A.	and
B.	pos
C.	sop
D.	nand
Answer» B. pos

276.	A variable on its own or in its complemented form is known as a
A.	product term
B.	literal
C.	sum term
D.	word
Answer» B. literal

277.	Canonical form is a unique way of representing
A.	sop
B.	minterm
C.	boolean expressions
D.	pos
Answer» C. boolean expressions

278.	There are Minterms for 3 variables (a, b, c).
A.	0
B.	2
C.	8
D.	1
Answer» C. 8

279.	Why is a demultiplexer called a data distributor?
A.	the input will be distributed to one of the outputs
B.	one of the inputs will be selected for the output
C.	the output will be distributed to one of the inputs
D.	single input gives single output
Answer» A. the input will be distributed to one of the outputs

280.	Most demultiplexers facilitate which type of conversion?
A.	decimal-to-hexadecimal
B.	single input, multiple outputs
C.	ac to dc
D.	odd parity to even parity
Answer» B. single input, multiple outputs

281.	In 1-to-4 demultiplexer, how many select lines are required?
A.	2
B.	3
C.	4
D.	5
Answer» A. 2

282.	In a multiplexer the output depends on its
A.	data inputs
B.	select inputs
C.	select outputs
D.	enable pin
Answer» B. select inputs

283.	In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be
A.	y0
B.	y1
C.	y2
D.	y3
Answer» D. y3

284.	How many select lines are required for a 1-to-8 demultiplexer?
A.	2
B.	3
C.	4
D.	5
Answer» B. 3

285.	How many AND gates are required for a 1-to-8 multiplexer?
A.	2
B.	6
C.	8
D.	5
Answer» C. 8

286.	Which IC is used for the implementation of 1-to-16 DEMUX?
A.	ic 74154
B.	ic 74155
C.	ic 74139
D.	ic 74138
Answer» A. ic 74154

287.	The word demultiplex means
A.	one into many
B.	many into one
C.	distributor
D.	one into many as well as distributor
Answer» D. one into many as well as distributor

288.	Why is a demultiplexer called a data distributor?
A.	the input will be distributed to one of the outputs
B.	one of the inputs will be selected for the output
C.	the output will be distributed to one of the inputs
D.	single input to single output
Answer» A. the input will be distributed to one of the outputs

289.	In a multiplexer the output depends on its
A.	data inputs
B.	select inputs
C.	select outputs
D.	enable pin
Answer» B. select inputs

290.	In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be
A.	y0
B.	y1
C.	y2
D.	y3
Answer» B. y1

291.	In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be
A.	y0
B.	y1
C.	y2
D.	y3
Answer» D. y3

292.	What is the addition of the binary numbers 11011011010 and 010100101?
A.	0111001000
B.	1100110110
C.	11101111111
D.	10011010011
Answer» C. 11101111111

293.	Perform binary addition: 101101 + 011011 = ?
A.	011010
B.	1010100
C.	101110
D.	1001000
Answer» D. 1001000

294.	Binary subtraction of 100101 – 011110 is
A.	000111
B.	111000
C.	010101
D.	101010
Answer» A. 000111

295.	Perform multiplication of the binary numbers: 01001 × 01011 = ?
A.	001100011
B.	110011100
C.	010100110
D.	101010111
Answer» A. 001100011

296.	100101 × 0110 = ?
A.	1011001111
B.	0100110011
C.	101111110
D.	0110100101
Answer» C. 101111110

297.	On multiplication of (10.10) and (01.01), we get
A.	101.0010
B.	0010.101
C.	011.0010
D.	110.0011
Answer» C. 011.0010

298.	Divide the binary numbers: 111101 ÷ 1001 and find the remainder
A.	0010
B.	1010
C.	1100
D.	0011
Answer» D. 0011

299.	Divide the binary number (011010000) by (0101) and find the quotient
A.	100011
B.	101001
C.	110010
D.	010001
Answer» A. 100011

301.	Which of the following flip-flop is used by the ring counter?
A.	d flip-flops
B.	sr flip-flops
C.	jk flip-flops
D.	t flip-flops
Answer» A. d flip-flops

302.	‘shift_reg’ is used to initialize the
A.	lsb
B.	msb
C.	register type
D.	register bits
Answer» B. msb

303.	How many types of shift operators are there in VHDL?
A.	three
B.	four
C.	five
D.	six
Answer» D. six

304.	How many types of the data type are there in the ring counter?
A.	one
B.	two
C.	three
D.	more than three
Answer» D. more than three

305.	In counter universal clock is not used.
A.	synchronous counter
B.	asynchronous counter
C.	decade counter
D.	ring counter
Answer» B. asynchronous counter

306.	Synchronous counter use global clock, unlike asynchronous counter.
A.	one
B.	two
C.	three
D.	zero
Answer» A. one

307.	How many different states does a decade counter count?
A.	eight
B.	nine
C.	ten
D.	eleven
Answer» C. ten

308.	Output values of Moore type FSM are determined by its
A.	input values
B.	output values
C.	clock input
D.	current state
Answer» D. current state

309.	What happens if the input is high in FSM?
A.	change of state
B.	no transition in state
C.	remains in a single state
D.	invalid state
Answer» A. change of state

310.	What happens if the input is low in FSM?
A.	change of state
B.	no transition in state
C.	remains in a single state
D.	invalid state
Answer» B. no transition in state

311.	. In FSM diagram what does circle represent?
A.	change of state
B.	state
C.	output value
D.	initial state
Answer» B. state

312.	In the FSM diagram, what does arrow between the circles represent?
A.	change of state
B.	state
C.	output value
D.	initial state
Answer» A. change of state

313.	. In the FSM diagram, what does the information below the line in the circle represent?
A.	change of state
B.	state
C.	output value
D.	initial state
Answer» C. output value

314.	Moore machine has states than a mealy machine.
A.	fewer
B.	more
C.	equal
D.	negligible
Answer» B. more

315.	State transition happens in every clock cycle.
A.	once
B.	twice
C.	thrice
D.	four times
Answer» A. once

316.	Output values of mealy type FSM are determined by its
A.	input values
B.	output values
C.	both input values and current state
D.	current state
Answer» C. both input values and current state

317.	What kind of output does mealy machine produce?
A.	asynchronous
B.	synchronous
C.	level
D.	pulsed
Answer» A. asynchronous

318.	States in FSM are represented by
A.	bits
B.	bytes
C.	word
D.	character
Answer» A. bits

319.	What is the first step in writing the VHDL for an FSM?
A.	to define the vhdl entity
B.	naming the entity
C.	defining the data type
D.	creating the states
Answer» A. to define the vhdl entity

320.	Which of the following react faster to inputs?
A.	sequencer
B.	generators
C.	mealy machines
D.	moore machines
Answer» C. mealy machines

321.	What is the first state of FSM?
A.	wait loop state
B.	initial state
C.	output state
D.	activate pulse state
Answer» B. initial state

322.	Mealy machines have states than Moore machine.
A.	fewer
B.	more
C.	equal
D.	negligible
Answer» A. fewer

323.	In mealy type FSM, the path is labelled by which of the following?
A.	inputs
B.	outputs
C.	both inputs and outputs
D.	current state
Answer» C. both inputs and outputs

324.	The process statement used in combinational circuits is called process.
A.	combinational
B.	clocked
C.	unclocked
D.	sequential
Answer» A. combinational

326.	Shift registers comprise of which flip-flops?
A.	d flip-flops
B.	sr flip-flops
C.	jk flip-flops
D.	t flip-flops
Answer» A. d flip-flops

327.	In serial input serial output register, the data of is accessed by the circuit.
A.	last flip-flop
B.	first flip-flop
C.	all flip-flops
D.	no flip-flop
Answer» B. first flip-flop

328.	In PIPO shift register, parallel data can be taken out by
A.	using the q output of the first flip-flop
B.	using the q output of the last flip-flop
C.	using the q output of the second flip-flop
D.	using the q output of each flip-flop
Answer» D. using the q output of each flip-flop

329.	Four bits shift register enables shift control signal in how many clock pulses?
A.	two clock pulses
B.	three clock pulses
C.	four clock pulses
D.	five clock pulses
Answer» C. four clock pulses

330.	Time taken by the shift register to transfer the content is called
A.	clock duration
B.	bit duration
C.	word duration
D.	duration
Answer» C. word duration

331.	Transfer of one bit of information at a time is called
A.	rotating
B.	serial transfer
C.	parallel transfer
D.	shifting
Answer» B. serial transfer

332.	In gated D latch, which of the following is the input symbol?
A.	d
B.	q
C.	en
D.	clk
Answer» A. d

333.	Which of the following is true about packages?
A.	package is collection of libraries
B.	library is collection of packages
C.	package is collection of entities
D.	entity is collection of packages
Answer» B. library is collection of packages

334.	A package may consist of design units.
A.	2
B.	3
C.	4
D.	5
Answer» A. 2

335.	Any item declared in a package declaration section are visible to
A.	every design unit
B.	package body only
C.	library containing that package
D.	design unit that use the package
Answer» D. design unit that use the package

336.	Which of the following is not a in-built package in VHDL?
A.	std_logic_1164
B.	textio
C.	standard
D.	std
Answer» D. std

337.	Packages increases of the code.
A.	reusability
B.	readability
C.	managing
D.	resolution
Answer» A. reusability

338.	Which of the following can’t have multiple assignments or drivers?
A.	std_logic
B.	integer
C.	std_ulogic
D.	bit
Answer» C. std_ulogic

339.	Which of the following is a not a characteristics of combinational circuits?
A.	the output of combinational circuit depends on present input
B.	there is no use of clock signal in combinational circuits
C.	the output of combinational circuit depends on previous output
D.	there is no storage element in combinational circuit
Answer» C. the output of combinational circuit depends on previous output

340.	Which of the following is not a combinational circuit?
A.	adder
B.	code convertor
C.	multiplexer
D.	counter
Answer» D. counter

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