| 1. | The format is usually used to store data. |
| A. | bcd |
| B. | decimal |
| C. | hexadecimal |
| D. | octal |
| Answer» A. bcd | |
| Explanation: the data usually used by computers have to be stored and represented in a particular format for ease of use. | |
| 2. | The 8-bit encoding format used to store data in a computer is |
| A. | ascii |
| B. | ebcdic |
| C. | anci |
| D. | uscii |
| Answer» B. ebcdic | |
| Explanation: the data to be stored in the computers have to be encoded in a particular way so as to provide secure processing of the data. | |
| 3. | A source program is usually in |
| A. | assembly language |
| B. | machine level language |
| C. | high-level language |
| D. | natural language |
| Answer» C. high-level language | |
| Explanation: the program written and before being compiled or assembled is called as a source program. | |
| 4. | Which memory device is generally made of semiconductors? |
| A. | ram |
| B. | hard-disk |
| C. | floppy disk |
| D. | cd disk |
| Answer» A. ram | |
| Explanation: memory devices are usually made of semiconductors for faster manipulation of the contents. | |
| 5. | The small extremely fast, RAM’s are called as |
| A. | cache |
| B. | heaps |
| C. | accumulators |
| D. | stacks |
| Answer» A. cache | |
| Explanation: these small and fast memory devices are compared to ram because they optimize the performance of the system and they only keep files which are required by the current process in them | |
| 6. | The ALU makes use of to store the intermediate results. |
| A. | accumulators |
| B. | registers |
| C. | heap |
| D. | stack |
| Answer» A. accumulators | |
| Explanation: the alu is the computational center of the cpu. it performs all mathematical and logical operations. in order to perform better, it uses some internal memory spaces to store immediate results. | |
| 7. | The control unit controls other units by generating |
| A. | control signals |
| B. | timing signals |
| C. | transfer signals |
| D. | command signals |
| Answer» B. timing signals | |
| Explanation: this unit is used to control and coordinate between the various parts and components of the cpu. | |
| 8. | are numbers and encoded characters, generally used as operands. |
| A. | input |
| B. | data |
| C. | information |
| D. | stored values |
| Answer» B. data | |
| Explanation: none. | |
| 9. | The Input devices can send information to the processor. |
| A. | when the sin status flag is set |
| B. | when the data arrives regardless of the sin flag |
| C. | neither of the cases |
| D. | either of the cases |
| Answer» A. when the sin status flag is set | |
| Explanation: the input devices use buffers to store the data received and when the buffer has some data it sends it to the processor. | |
| 10. | bus structure is usually used to connect I/O devices. |
| A. | single bus |
| B. | multiple bus |
| C. | star bus |
| D. | rambus |
| Answer» A. single bus | |
| Explanation: bus is a bunch of wires which carry address, control signals and data. it is used to connect various components of the computer. | |
| 11. | The I/O interface required to connect the I/O device to the bus consists of |
| A. | address decoder and registers |
| B. | control circuits |
| C. | address decoder, registers and control circuits |
| D. | only control circuits |
| Answer» C. address decoder, registers and control circuits | |
| Explanation: the i/o devices are connected to the cpu via bus and to interact with the bus they have an interface. | |
| 12. | To reduce the memory access time we generally make use of |
| A. | heaps |
| B. | higher capacity ram’s |
| C. | sdram’s |
| D. | cache’s |
| Answer» D. cache’s | |
| Explanation: the time required to access a part of the memory for data retrieval. | |
| 13. | is generally used to increase the apparent size of physical memory. |
| A. | secondary memory |
| B. | virtual memory |
| C. | hard-disk |
| D. | disks |
| Answer» B. virtual memory | |
| Explanation: virtual memory is like an extension to the existing memory. | |
| 14. | MFC stands for |
| A. | memory format caches |
| B. | memory function complete |
| C. | memory find command |
| D. | mass format command |
| Answer» B. memory function complete | |
| Explanation: this is a system command enabled when a memory function is completed by a process. | |
| 15. | The time delay between two successive initiations of memory operation |
| A. | memory access time |
| B. | memory search time |
| C. | memory cycle time |
| D. | instruction delay |
| Answer» C. memory cycle time | |
| Explanation: the time is taken to finish one task and to start another. | |
| 16. | The decoded instruction is stored in |
| A. | ir |
| B. | pc |
| C. | registers |
| D. | mdr |
| Answer» A. ir | |
| Explanation: the instruction after obtained from the pc, is decoded and operands are fetched and stored in the ir. | |
| 17. | Which registers can interact with the secondary storage? |
| A. | mar |
| B. | pc |
| C. | ir |
| D. | r0 |
| Answer» A. mar | |
| Explanation: mar can interact with secondary storage in order to fetch data from it. | |
| 18. | During the execution of a program which gets initialized first? |
| A. | mdr |
| B. | ir |
| C. | pc |
| D. | mar |
| Answer» C. pc | |
| Explanation: for the execution of a process first the instruction is placed in the pc. | |
| 19. | Which of the register/s of the processor is/are connected to Memory Bus? |
| A. | pc |
| B. | mar |
| C. | ir |
| D. | both pc and mar |
| Answer» B. mar | |
| Explanation: mar is connected to the memory bus in order to access the memory. | |
| 20. | ISP stands for |
| A. | instruction set processor |
| B. | information standard processing |
| C. | interchange standard protocol |
| D. | interrupt service procedure |
| Answer» A. instruction set processor | |
| Explanation: none. | |
| 21. | The internal components of the processor are connected by |
| A. | processor intra-connectivity circuitry |
| B. | processor bus |
| C. | memory bus |
| D. | rambus |
| Answer» B. processor bus | |
| Explanation: the processor bus is used to connect the various parts in order to provide a direct connection to the cpu. | |
| 22. | is used to choose between incrementing the PC or performing ALU operations. |
| A. | conditional codes |
| B. | multiplexer |
| C. | control unit |
| D. | none of the mentioned |
| Answer» B. multiplexer | |
| Explanation: the multiplexer circuit is used to choose between the two as it can give different results based on the input. | |
| 23. | The registers, ALU and the interconnection between them are collectively called as |
| A. | process route |
| B. | information trail |
| C. | information path |
| D. | data path |
| Answer» D. data path | |
| Explanation: the operational and | |
| 24. | is used to store data in registers. |
| A. | d flip flop |
| B. | jk flip flop |
| C. | rs flip flop |
| D. | none of the mentioned |
| Answer» A. d flip flop | |
| Explanation: none. | |
| 26. | are used to overcome the difference in data transfer speeds of various devices. | |
| A. | speed enhancing circuitory | |
| B. | bridge circuits | |
| C. | multiple buses | |
| D. | buffer registers | |
| Answer» D. buffer registers | ||
| Explanation: by using buffer registers, the processor sends the data to the i/o device at the processor speed and the data gets stored in the buffer. after that the data gets sent to or from the buffer to the devices at the device speed. | ||
| 27. | To extend the connectivity of the processor bus we use |
| A. | pci bus |
| B. | scsi bus |
| C. | controllers |
| D. | multiple bus |
| Answer» A. pci bus | |
| Explanation: pci bus is used to connect other peripheral devices that require a direct connection with the processor. | |
| 28. | IBM developed a bus standard for their line of computers ‘PC AT’ called |
| A. | ib bus |
| B. | m-bus |
| C. | isa |
| D. | none of the mentioned |
| Answer» C. isa | |
| Explanation: none. | |
| 29. | The bus used to connect the monitor to the CPU is |
| A. | pci bus |
| B. | scsi bus |
| C. | memory bus |
| D. | rambus |
| Answer» B. scsi bus | |
| Explanation: scsi bus is usually used to connect video devices to the processor. | |
| 30. | ANSI stands for |
| A. | american national standards institute |
| B. | american national standard interface |
| C. | american network standard interfacing |
| D. | american network security interrupt |
| Answer» A. american national standards institute view more info and meaning of ANSI | |
| Explanation: none. | |
| 31. | register Connected to the Processor bus is a single-way transfer capable. |
| A. | pc |
| B. | ir |
| C. | temp |
| D. | z |
| Answer» D. z | |
| Explanation: the z register is a special register which can interact with the processor bus only. | |
| 32. | In multiple Bus organisation, the registers are collectively placed and referred as |
| A. | set registers |
| B. | register file |
| C. | register block |
| D. | map registers |
| Answer» B. register file | |
| Explanation: none. | |
| 33. | The main advantage of multiple bus organisation over a single bus is |
| A. | reduction in the number of cycles for execution |
| B. | increase in size of the registers |
| C. | better connectivity |
| D. | none of the mentioned |
| Answer» A. reduction in the number of cycles for execution | |
| Explanation: none. | |
| 34. | The ISA standard Buses are used to connect |
| A. | ram and processor |
| B. | gpu and processor |
| C. | harddisk and processor |
| D. | cd/dvd drives and processor |
| Answer» C. harddisk and processor | |
| Explanation: none. | |
| 35. | During the execution of the instructions, a copy of the instructions is placed in the |
| A. | register |
| B. | ram |
| C. | system heap |
| D. | cache |
| Answer» D. cache | |
| Explanation: none. | |
| 36. | Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster? |
| A. | a |
| B. | b |
| C. | both take the same time |
| D. | insufficient information |
| Answer» A. a | |
| Explanation: the performance of a system can be found out using the basic performance formula. | |
| 37. | A processor performing fetch or decoding of different instruction during the execution of another instruction is called |
| A. | super-scaling |
| B. | pipe-lining |
| C. | parallel computation |
| D. | none of the mentioned |
| Answer» B. pipe-lining | |
| Explanation: pipe-lining is the process of improving the performance of the system by processing different instructions at the same time, with only one instruction performing one specific operation. | |
| 38. | The clock rate of the processor can be improved by |
| A. | improving the ic technology of the logic circuits |
| B. | reducing the amount of processing done in one step |
| C. | by using the overclocking method |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the clock rate(frequency of the processor) is the hardware dependent quantity it is fixed for a given processor. | |
| 39. | An optimizing Compiler does |
| A. | better compilation of the given piece of code |
| B. | takes advantage of the type of processor and reduces its process time |
| C. | does better memory management |
| D. | none of the mentioned |
| Answer» B. takes advantage of the type of processor and reduces its process time | |
| Explanation: an optimizing compiler is a compiler designed for the specific purpose of increasing the operation speed of the processor by reducing the time taken to compile the program instructions. | |
| 40. | SPEC stands for |
| A. | standard performance evaluation code |
| B. | system processing enhancing code |
| C. | system performance evaluation corporation |
| D. | standard processing enhancement corporation |
| Answer» C. system performance evaluation corporation | |
| Explanation: spec is a corporation that started to standardize the evaluation method of a system’s performance. | |
| 41. | As of 2000, the reference system to find the performance of a system is |
| A. | ultra sparc 10 |
| B. | sun sparc |
| C. | sun ii |
| D. | none of the mentioned |
| Answer» A. ultra sparc 10 | |
| Explanation: in spec system of measuring a system’s performance, a system is used as a reference against which other systems are compared and performance is determined. | |
| 42. | If a processor clock is rated as 1250 million cycles per second, then its clock period is |
| A. | 1.9 * 10-10 sec |
| B. | 1.6 * 10-9 sec |
| C. | 1.25 * 10-10 sec |
| D. | 8 * 10-10 sec |
| Answer» D. 8 * 10-10 sec | |
| Explanation: none. | |
| 43. | If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is (Where S is a term of the Basic performance equation)? |
| A. | 3 |
| B. | ~2 |
| C. | ~1 |
| D. | 6 |
| Answer» C. ~1 | |
| Explanation: s is the number of steps | |
| 44. | CISC stands for |
| A. | complete instruction sequential compilation |
| B. | computer integrated sequential compiler |
| C. | complex instruction set computer |
| D. | complex instruction sequential compilation |
| Answer» C. complex instruction set computer view more info and meaning of CISC | |
| Explanation: cisc is a type of system architecture where complex instructions | |
| 45. | In the case of, Zero-address instruction method the operands are stored in |
| A. | registers |
| B. | accumulators |
| C. | push down stack |
| D. | cache |
| Answer» C. push down stack | |
| Explanation: in this case, the operands are implicitly loaded onto the alu. | |
| 46. | As of 2000, the reference system to find the SPEC rating are built with Processor. |
| A. | intel atom sparc 300mhz |
| B. | ultra sparc -iii 300mhz |
| C. | amd neutrino series |
| D. | asus a series 450 mhz |
| Answer» B. ultra sparc -iii 300mhz | |
| Explanation: none. | |
| 47. | The instruction, Add #45,R1 does |
| A. | adds the value of 45 to the address of r1 and stores 45 in that address |
| B. | adds 45 to the value of r1 and stores it in r1 |
| C. | finds the memory location 45 and adds that content to that of r1 |
| D. | none of the mentioned |
| Answer» B. adds 45 to the value of r1 and stores it in r1 | |
| Explanation: the instruction is using immediate addressing mode hence the value is stored in the location 45 is added. | |
| 48. | The addressing mode which makes use of in-direction pointers is |
| A. | indirect addressing mode |
| B. | index addressing mode |
| C. | relative addressing mode |
| D. | offset addressing mode |
| Answer» A. indirect addressing mode | |
| Explanation: in this addressing mode, the value of the register serves as another memory location and hence we use pointers to get the data. | |
| 49. | In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is |
| A. | ea = 5+r1 |
| B. | ea = r1 |
| C. | ea = [r1] |
| D. | ea = 5+[r1] |
| Answer» D. ea = 5+[r1] | |
| Explanation: this instruction is in base with offset addressing mode. | |
| 50. | The addressing mode/s, which uses the PC instead of a general purpose register is |
| A. | indexed with offset |
| B. | relative |
| C. | direct |
| D. | both indexed with offset and direct |
| Answer» B. relative | |
| Explanation: in this, the contents of the pc are directly incremented. | |
| 51. | The addressing mode, where you directly specify the operand value is |
| A. | immediate |
| B. | direct |
| C. | definite |
| D. | relative |
| Answer» A. immediate | |
| Explanation: none. | |
| 52. | addressing mode is most suitable to change the normal sequence of execution of instructions. |
| A. | relative |
| B. | indirect |
| C. | index with offset |
| D. | immediate |
| Answer» A. relative | |
| Explanation: the relative addressing mode is used for this since it directly updates the pc. | |
| 53. | Which method/s of representation of numbers occupies a large amount of memory than others? |
| A. | sign-magnitude |
| B. | 1’s complement |
| C. | 2’s complement |
| D. | 1’s & 2’s compliment |
| Answer» A. sign-magnitude | |
| Explanation: it takes more memory as one bit used up to store the sign. | |
| 54. | Which method of representation has two representations for ‘0’? |
| A. | sign-magnitude |
| B. | 1’s complement |
| C. | 2’s complement |
| D. | none of the mentioned |
| Answer» A. sign-magnitude | |
| Explanation: one is positive and one for negative. | |
| 55. | When we perform subtraction on -7 and 1 the answer in 2’s complement form is |
| A. | 1010 |
| B. | 1110 |
| C. | 0110 |
| D. | 1000 |
| Answer» D. 1000 | |
| Explanation: first the 2’s complement is found and that is added to the number and the overflow is ignored. | |
| 56. | The processor keeps track of the results of its operations using flags called |
| A. | conditional code flags |
| B. | test output flags |
| C. | type flags |
| D. | none of the mentioned |
| Answer» A. conditional code flags | |
| Explanation: these flags are used to indicate if there is an overflow or carry or zero result occurrence. | |
| 57. | The register used to store the flags is called as |
| A. | flag register |
| B. | status register |
| C. | test register |
| D. | log register |
| Answer» B. status register | |
| Explanation: the status register stores the condition codes of the system. | |
| 58. | In some pipelined systems, a different instruction is used to add to numbers which can affect the flags upon |
| A. | and gate |
| B. | nand gate |
| C. | nor gate |
| D. | xor gate |
| Answer» D. xor gate | |
| Explanation: none. | |
| 59. | The most efficient method followed by computers to multiply two unsigned numbers is |
| A. | booth algorithm |
| B. | bit pair recording of multipliers |
| C. | restoring algorithm |
| D. | non restoring algorithm |
| Answer» B. bit pair recording of multipliers | |
| Explanation: none. | |
| 60. | For the addition of large integers, most of the systems make use of |
| A. | fast adders |
| B. | full adders |
| C. | carry look-ahead adders |
| D. | none of the mentioned |
| Answer» C. carry look-ahead adders | |
| Explanation: in this method, the carries for each step are generated first. | |
| 61. | In a normal n-bit adder, to find out if an overflow as occurred we make use of |
| A. | counter |
| B. | flip flop |
| C. | shift register |
| D. | push down stack |
| Answer» C. shift register | |
| Explanation: the shift registers are used to store the multiplied answer. | |
| 62. | The smallest entity of memory is called |
| A. | cell |
| B. | block |
| C. | instance |
| D. | unit |
| Answer» A. cell | |
| Explanation: each data is made up of a number of units. | |
| 63. | The collection of the above mentioned entities where data is stored is called |
| A. | block |
| B. | set |
| C. | word |
| D. | byte |
| Answer» C. word | |
| Explanation: each readable part of the data is called blocks. | |
| 64. | If a system is 64 bit machine, then the length of each word will be |
| A. | 4 bytes |
| B. | 8 bytes |
| C. | 16 bytes |
| D. | 12 bytes |
| Answer» B. 8 bytes | |
| Explanation: a 64 bit system means, that at a time 64 bit instruction can be executed. | |
| 65. | The type of memory assignment used in Intel processors is |
| A. | little endian |
| B. | big endian |
| C. | medium endian |
| D. | none of the mentioned |
| Answer» A. little endian | |
| Explanation: the method of address allocation to data to be stored is called as memory assignment. | |
| 66. | When using the Big Endian assignment to store a number, the sign bit of the number is stored in |
| A. | the higher order byte of the word |
| B. | the lower order byte of the word |
| C. | can’t say |
| D. | none of the mentioned |
| Answer» A. the higher order byte of the word | |
| Explanation: none. | |
| 67. | To get the physical address from the logical address generated by CPU we use |
| A. | mar |
| B. | mmu |
| C. | overlays |
| D. | tlb |
| Answer» B. mmu | |
| Explanation: memory management unit, is used to add the offset to the logical address generated by the cpu to get the physical address. | |
| 68. | method is used to map logical addresses of variable length onto physical memory. |
| A. | paging |
| B. | overlays |
| C. | segmentation |
| D. | paging with segmentation |
| Answer» C. segmentation | |
| Explanation: segmentation is a process in which memory is divided into groups of variable length called segments. | |
| 69. | During the transfer of data between the processor and memory we use |
| A. | cache |
| B. | tlb |
| C. | buffers |
| D. | registers |
| Answer» D. registers | |
| Explanation: none. | |
| 70. | Physical memory is divided into sets of finite size called as |
| A. | frames |
| B. | pages |
| C. | blocks |
| D. | vectors |
| Answer» A. frames | |
| Explanation: none. | |
| 71. | Add #%01011101,R1 , when this instruction is executed then |
| A. | the binary addition between the operands takes place |
| B. | the numerical value represented by the binary value is added to the value of r1 |
| C. | the addition doesn’t take place, whereas this is similar to a mov instruction |
| D. | none of the mentioned |
| Answer» A. the binary addition between the operands takes place | |
| Explanation: this performs operations in binary mode directly. | |
| 72. | If we want to perform memory or arithmetic operations on data in Hexa- decimal mode then we use symbol before the operand. |
| A. | ~ |
| B. | ! |
| C. | $ |
| D. | * |
| Answer» C. $ | |
| Explanation: none. | |
| 73. | When generating physical addresses from a logical address the offset is stored in |
| A. | translation look-aside buffer |
| B. | relocation register |
| C. | page table |
| D. | shift register |
| Answer» B. relocation register | |
| Explanation: in the mmu the relocation register stores the offset address. | |
| 74. | The technique used to store programs larger than the memory is |
| A. | overlays |
| B. | extension registers |
| C. | buffers |
| D. | both extension registers and buffers |
| Answer» A. overlays | |
| Explanation: in this, only a part of the program getting executed is stored on the memory and later swapped in for the other part. | |
| 76. | Does the Load instruction do the following operation/s? | |
| A. | loads the contents of a disc onto a memory location | |
| B. | loads the contents of a location onto the accumulators | |
| C. | load the contents of the pcb onto the register | |
| D. | none of the mentioned | |
| Answer» B. loads the contents of a location onto the accumulators | ||
| Explanation: the load instruction is basically used to load the contents of a memory location onto a register. | ||
| 77. | Complete the following analogy:- Registers are to RAM’s as Cache’s are to |
| A. | system stacks |
| B. | overlays |
| C. | page table |
| D. | tlb |
| Answer» D. tlb | |
| Explanation: none. | |
| 78. | The BOOT sector files of the system are stored in |
| A. | harddisk |
| B. | rom |
| C. | ram |
| D. | fast solid state chips in the motherboard |
| Answer» B. rom | |
| Explanation: the files which are required for the starting up of a system are stored on the rom. | |
| 79. | The transfer of large chunks of data with the involvement of the processor is done by |
| A. | dma controller |
| B. | arbitrator |
| C. | user system programs |
| D. | none of the mentioned |
| Answer» A. dma controller | |
| Explanation: this mode of transfer involves the transfer of a large block of data from the memory. | |
| 80. | Which of the following techniques used to effectively utilize main memory? |
| A. | address binding |
| B. | dynamic linking |
| C. | dynamic loading |
| D. | both dynamic linking and loading |
| Answer» C. dynamic loading | |
| Explanation: in this method only when the routine is required is loaded and hence saves memory. | |
| 81. | RTN stands for |
| A. | register transfer notation |
| B. | register transmission notation |
| C. | regular transmission notation |
| D. | regular transfer notation |
| Answer» A. register transfer notation | |
| Explanation: this is the way of writing the assembly language code with the help of register notations. | |
| 82. | The instruction, Add Loc,R1 in RTN is |
| A. | addsetcc loc+r1 |
| B. | r1=loc+r1 |
| C. | not possible to write in rtn |
| D. | r1<-[loc]+[r1] |
| Answer» D. r1<-[loc]+[r1] | |
| Explanation: none. | |
| 83. | Can you perform an addition on three operands simultaneously in ALN using Add instruction? |
| A. | yes |
| B. | not possible using add, we’ve to use addsetcc |
| C. | not permitted |
| D. | none of the mentioned |
| Answer» C. not permitted | |
| Explanation: you cannot perform an addition on three operands simultaneously because the third operand is where the result is stored. | |
| 84. | The instruction, Add R1,R2,R3 in RTN is |
| A. | r3=r1+r2+r3 |
| B. | r3<-[r1]+[r2]+[r3] |
| C. | r3=[r1]+[r2] |
| D. | r3<-[r1]+[r2] |
| Answer» D. r3<-[r1]+[r2] | |
| Explanation: in rtn the first operand is the destination and the second operand is the source. | |
| 85. | In a system, which has 32 registers the register id is long. |
| A. | 16 bit |
| B. | 8 bits |
| C. | 5 bits |
| D. | 6 bits |
| Answer» C. 5 bits | |
| Explanation: the id is the name tag given to each of the registers and used to identify them. | |
| 86. | While using the iterative construct (Branching) in execution instruction is used to check the condition. |
| A. | testandset |
| B. | branch |
| C. | testcondn |
| D. | none of the mentioned |
| Answer» B. branch | |
| Explanation: branch instruction is used to check the test condition and to perform the memory jump with the help of offset. | |
| 87. | The condition flag Z is set to 1 to indicate |
| A. | the operation has resulted in an error |
| B. | the operation requires an interrupt call |
| C. | the result is zero |
| D. | there is no empty register available |
| Answer» C. the result is zero | |
| Explanation: this condition flag is used | |
| 88. | converts the programs written in assembly language into machine instructions. |
| A. | machine compiler |
| B. | interpreter |
| C. | assembler |
| D. | converter |
| Answer» C. assembler | |
| Explanation: an assembler is a software used to convert the programs into machine instructions. | |
| 89. | The instructions like MOV or ADD are called as |
| A. | op-code |
| B. | operators |
| C. | commands |
| D. | none of the mentioned |
| Answer» A. op-code | |
| Explanation: this op – codes tell the | |
| 90. | The assembler directive EQU, when used in the instruction: Sum EQU 200 does |
| A. | finds the first occurrence of sum and assigns value 200 to it |
| B. | replaces every occurrence of sum with 200 |
| C. | re-assigns the address of sum by adding 200 to its original address |
| D. | assigns 200 bytes of memory starting the location of sum |
| Answer» B. replaces every occurrence of sum with 200 | |
| Explanation: this basically is used to replace the variable with a constant value. | |
| 91. | The directive used to perform initialization before the execution of the code is |
| A. | reserve |
| B. | store |
| C. | dataword |
| D. | equ |
| Answer» C. dataword | |
| Explanation: none. | |
| 92. | directive is used to specify and assign the memory required for the block of code. |
| A. | allocate |
| B. | assign |
| C. | set |
| D. | reserve |
| Answer» D. reserve | |
| Explanation: this instruction is used to allocate a block of memory and to store the object code of the program there. | |
| 93. | directive specifies the end of execution of a program. |
| A. | end |
| B. | return |
| C. | stop |
| D. | terminate |
| Answer» B. return | |
| Explanation: this instruction directive is used to terminate the program execution. | |
| 94. | The last statement of the source program should be |
| A. | stop |
| B. | return |
| C. | op |
| D. | end |
| Answer» D. end | |
| Explanation: this enables the processor to load some other process. | |
| 95. | The assembler stores all the names and their corresponding values in |
| A. | special purpose register |
| B. | symbol table |
| C. | value map set |
| D. | none of the mentioned |
| Answer» B. symbol table | |
| Explanation: the table where the assembler stores the variable names along with their corresponding memory locations and values. | |
| 96. | The assembler stores the object code in |
| A. | main memory |
| B. | cache |
| C. | ram |
| D. | magnetic disk |
| Answer» D. magnetic disk | |
| Explanation: after compiling the object code, the assembler stores it in the magnetic disk and waits for further execution. | |
| 97. | The utility program used to bring the object code into memory for execution is |
| A. | loader |
| B. | fetcher |
| C. | extractor |
| D. | linker |
| Answer» A. loader | |
| Explanation: the program is used to load the program into memory. | |
| 98. | To overcome the problems of the assembler in dealing with branching code we use |
| A. | interpreter |
| B. | debugger |
| C. | op-assembler |
| D. | two-pass assembler |
| Answer» D. two-pass assembler | |
| Explanation: this creates entries into the symbol table first and then creates the object code. | |
| 99. | The return address of the Sub-routine is pointed to by |
| A. | ir |
| B. | pc |
| C. | mar |
| D. | special memory registers |
| Answer» B. pc | |
| Explanation: the return address from the subroutine is pointed to by the pc. | |
| 101. | What is subroutine nesting? |
| A. | having multiple subroutines in a program |
| B. | using a linking nest statement to put many subroutines under the same name |
| C. | having one routine call the other |
| D. | none of the mentioned |
| Answer» C. having one routine call the other | |
| Explanation: none. | |
| 102. | The order in which the return addresses are generated and used is |
| A. | lifo |
| B. | fifo |
| C. | random |
| D. | highest priority |
| Answer» A. lifo | |
| Explanation: that is the routine called first is returned first. | |
| 103. | In case of nested subroutines the return addresses are stored in |
| A. | system heap |
| B. | special memory buffers |
| C. | processor stack |
| D. | registers |
| Answer» C. processor stack | |
| Explanation: in this case, there will be more number of return addresses it is stored on the processor stack. | |
| 104. | The appropriate return addresses are obtained with the help of in case of nested routines. |
| A. | mar |
| B. | mdr |
| C. | buffers |
| D. | stack-pointers |
| Answer» D. stack-pointers | |
| Explanation: the pointers are used to point to the location on the stack where the address is stored. | |
| 105. | When parameters are being passed on to the subroutines they are stored in |
| A. | registers |
| B. | memory locations |
| C. | processor stacks |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: in the case of, parameter passing the data can be stored on any of the storage space. | |
| 106. | The most efficient way of handling parameter passing is by using |
| A. | general purpose registers |
| B. | stacks |
| C. | memory locations |
| D. | none of the mentioned |
| Answer» A. general purpose registers | |
| Explanation: by using general purpose registers for the parameter passing we make the process more efficient. | |
| 107. | The most Flexible way of logging the return addresses of the subroutines is by using |
| A. | registers |
| B. | stacks |
| C. | memory locations |
| D. | none of the mentioned |
| Answer» B. stacks | |
| Explanation: the stacks are used as logs for return addresses of the subroutines. | |
| 108. | The private work space dedicated to a subroutine is called as |
| A. | system heap |
| B. | reserve |
| C. | stack frame |
| D. | allocation |
| Answer» C. stack frame | |
| Explanation: this work space is where the intermediate values of the subroutines are stored. | |
| 109. | If the subroutine exceeds the private space allocated to it then the values are pushed onto |
| A. | stack |
| B. | system heap |
| C. | reserve space |
| D. | stack frame |
| Answer» A. stack | |
| Explanation: if the allocated work space is exceeded then the data is pushed onto the system stack. | |
| 110. | pointer is used to point to parameters passed or local parameters of the subroutine. |
| A. | stack pointer |
| B. | frame pointer |
| C. | parameter register |
| D. | log register |
| Answer» B. frame pointer | |
| Explanation: this pointer is used to track the current position of the stack being used. | |
| 111. | The reserved memory or private space of the subroutine gets deallocated when |
| A. | the stop instruction is executed by the routine |
| B. | the pointer reaches the end of the space |
| C. | when the routine’s return statement is executed |
| D. | none of the mentioned |
| Answer» C. when the routine’s return statement is executed | |
| Explanation: the work space allocated to a subroutine gets deallocated when the routine is completed. | |
| 112. | The private space gets allocated to each subroutine when |
| A. | the first statement of the routine is executed |
| B. | when the context switch takes place |
| C. | when the routine gets called |
| D. | when the allocate instruction is executed |
| Answer» C. when the routine gets called | |
| Explanation: when the call statement is executed, simultaneously space also gets allocated. | |
| 113. | the most suitable data structure used to store the return addresses in the case of nested subroutines. |
| A. | heap |
| B. | stack |
| C. | queue |
| D. | list |
| Answer» B. stack | |
| Explanation: none. | |
| 114. | In the case of nested subroutines, the stack top is always |
| A. | the saved contents of the called sub routine |
| B. | the saved contents of the calling sub routine |
| C. | the return addresses of the called sub routine |
| D. | none of the mentioned |
| Answer» A. the saved contents of the called sub routine | |
| Explanation: none. | |
| 115. | The stack frame for each subroutine is present in |
| A. | main memory |
| B. | system heap |
| C. | processor stack |
| D. | none of the mentioned |
| Answer» C. processor stack | |
| Explanation: the memory for the work space is allocated from the processor stack. | |
| 116. | The data structure suitable for scheduling processes is |
| A. | list |
| B. | heap |
| C. | queue |
| D. | stack |
| Answer» C. queue | |
| Explanation: the queue data structure is generally used for scheduling as it is two directional. | |
| 117. | The sub-routine service procedure is similar to that of the interrupt service routine in |
| A. | method of context switch |
| B. | returning |
| C. | process execution |
| D. | method of context switch & process execution |
| Answer» D. method of context switch & process execution | |
| Explanation: the subroutine service procedure is the same as the interrupt service routine in all aspects, except the | |
| 118. | In memory-mapped I/O |
| A. | the i/o devices and the memory share the same address space |
| B. | the i/o devices have a separate address space |
| C. | the memory and i/o devices have an associated address space |
| D. | a part of the memory is specifically set aside for the i/o operation |
| Answer» A. the i/o devices and the memory share the same address space | |
| Explanation: its the different modes of accessing the i/o devices. | |
| 119. | The usual BUS structure used to connect the I/O devices is |
| A. | star bus structure |
| B. | multiple bus structure |
| C. | single bus structure |
| D. | node to node bus structure |
| Answer» C. single bus structure | |
| Explanation: bus is a collection of address, control and data lines used to connect the various devices of the computer. | |
| 120. | In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices. |
| A. | false |
| B. | true |
| Answer» B. true | |
| Explanation: this type of access is called as i/o mapped devices. | |
| 121. | The system is notified of a read or write operation by |
| A. | appending an extra bit of the address |
| B. | enabling the read or write bits of the devices |
| C. | raising an appropriate interrupt signal |
| D. | sending a special signal along the bus |
| Answer» D. sending a special signal along the bus | |
| Explanation: it is necessary for the processor to send a signal intimating the request as either read or write. | |
| 122. | To overcome the lag in the operating speeds of the I/O device and the processor we use |
| A. | buffer spaces |
| B. | status flags |
| C. | interrupt signals |
| D. | exceptions |
| Answer» B. status flags | |
| Explanation: the processor operating is much faster than that of the i/o devices, so by using the status flags the processor need not wait till the i/o operation is done. it can continue with its work until the status flag is set. | |
| 123. | The method of accessing the I/O devices by repeatedly checking the status flags is |
| A. | program-controlled i/o |
| B. | memory-mapped i/o |
| C. | i/o mapped |
| D. | none of the mentioned |
| Answer» A. program-controlled i/o | |
| Explanation: in this method, the processor constantly checks the status flags, and when it finds that the flag is set it performs the appropriate operation. | |
| 124. | The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is? |
| A. | exceptions |
| B. | signal handling |
| C. | interrupts |
| D. | dma |
| Answer» C. interrupts | |
| Explanation: this is a method of | |
| 126. | The method which offers higher speeds of I/O transfers is | |
| A. | interrupts | |
| B. | memory mapping | |
| C. | program-controlled i/o | |
| D. | dma | |
| Answer» D. dma | ||
| Explanation: in dma the i/o devices are directly allowed to interact with the memory without the intervention of the processor and the transfers take place in the form of blocks increasing the speed of operation. | ||
| 127. | The signal sent to the device from the processor to the device after receiving an interrupt is |
| A. | interrupt-acknowledge |
| B. | return signal |
| C. | service signal |
| D. | permission signal |
| Answer» A. interrupt-acknowledge | |
| Explanation: the processor upon receiving the interrupt should let the device know that its request is received. | |
| 128. | The time between the receiver of an interrupt and its service is |
| A. | interrupt delay |
| B. | interrupt latency |
| C. | cycle time |
| D. | switching time |
| Answer» B. interrupt latency | |
| Explanation: the delay in servicing of an interrupt happens due to the time is taken for contact switch to take place. | |
| 129. | A single Interrupt line can be used to service n different devices. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 130. | The resistor which is attached to the service line is called |
| A. | push-down resistor |
| B. | pull-up resistor |
| C. | break down resistor |
| D. | line resistor |
| Answer» B. pull-up resistor | |
| Explanation: this resistor is used to pull up the voltage of the interrupt service line. | |
| 131. | An interrupt that can be temporarily ignored is |
| A. | vectored interrupt |
| B. | non-maskable interrupt |
| C. | maskable interrupt |
| D. | high priority interrupt |
| Answer» C. maskable interrupt | |
| Explanation: the maskable interrupts are usually low priority interrupts which can be ignored if a higher priority process is being executed. | |
| 132. | Which interrupt is unmaskable? |
| A. | rst 5.5 |
| B. | rst 7.5 |
| C. | trap |
| D. | both rst 5.5 and 7.5 |
| Answer» C. trap | |
| Explanation: the trap is a non- maskable interrupt as it deals with the ongoing process in the processor. the trap is initiated by the process being executed due to lack of data required | |
| 133. | When dealing with multiple devices interrupts, which mechanism is easy to implement? |
| A. | polling method |
| B. | vectored interrupts |
| C. | interrupt nesting |
| D. | none of the mentioned |
| Answer» A. polling method | |
| Explanation: in this method, the processor checks the irq bits of all the devices, whichever is enabled first that device is serviced. | |
| 134. | The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is |
| A. | polling |
| B. | vectored interrupts |
| C. | interrupt nesting |
| D. | simultaneous requesting |
| Answer» B. vectored interrupts | |
| Explanation: none. | |
| 135. | In vectored interrupts, how does the device identify itself to the processor? |
| A. | by sending its device id |
| B. | by sending the machine code for the interrupt service routine |
| C. | by sending the starting address of the service routine |
| D. | none of the mentioned |
| Answer» C. by sending the starting address of the service routine | |
| Explanation: by sending the starting address of the routine the device ids the routine required and thereby identifying itself. | |
| 136. | The code sent by the device in vectored interrupt is long. |
| A. | upto 16 bits |
| B. | upto 32 bits |
| C. | upto 24 bits |
| D. | 4-8 bits |
| Answer» D. 4-8 bits | |
| Explanation: none. | |
| 137. | The starting address sent by the device in vectored interrupt is called as |
| A. | location id |
| B. | interrupt vector |
| C. | service location |
| D. | service id |
| Answer» B. interrupt vector | |
| Explanation: none. | |
| 138. | The processor indicates to the devices that it is ready to receive interrupts |
| A. | by enabling the interrupt request line |
| B. | by enabling the irq bits |
| C. | by activating the interrupt acknowledge line |
| D. | none of the mentioned |
| Answer» C. by activating the interrupt acknowledge line | |
| Explanation: when the processor activates the acknowledge line the devices send their interrupts to the processor. | |
| 139. | Which table handle stores the addresses of the interrupt handling sub- routines? |
| A. | interrupt-vector table |
| B. | vector table |
| C. | symbol link table |
| D. | none of the mentioned |
| Answer» A. interrupt-vector table | |
| Explanation: none. | |
| 140. | method is used to establish priority by serially connecting all devices that request an interrupt. |
| A. | vectored-interrupting |
| B. | daisy chain |
| C. | priority |
| D. | polling |
| Answer» B. daisy chain | |
| Explanation: in the daisy chain mechanism, all the devices are connected using a single request line and they’re serviced based on the interrupting device’s priority. | |
| 141. | In daisy chaining device 0 will pass the signal only if it has |
| A. | interrupt request |
| B. | no interrupt request |
| C. | both no interrupt and interrupt request |
| D. | none of the mentioned |
| Answer» B. no interrupt request | |
| Explanation: in daisy chaining since there is only one request line and only one acknowledges line, the acknowledge signal passes from device to device until the one with the interrupt is found. | |
| 142. | interrupt method uses register whose bits are set separately by interrupt signal for each device. |
| A. | parallel priority interrupt |
| B. | serial priority interrupt |
| C. | daisy chaining |
| D. | none of the mentioned |
| Answer» A. parallel priority interrupt | |
| Explanation: none. | |
| 143. | register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt. |
| A. | mass |
| B. | mark |
| C. | make |
| D. | mask |
| Answer» D. mask | |
| Explanation: none. | |
| 144. | The added output of the bits of the interrupt register and the mask register is set as an input of |
| A. | priority decoder |
| B. | priority encoder |
| C. | process id encoder |
| D. | multiplexer |
| Answer» B. priority encoder | |
| Explanation: in a parallel priority | |
| 145. | Interrupts initiated by an instruction is called as |
| A. | internal |
| B. | external |
| C. | hardware |
| D. | software |
| Answer» B. external | |
| Explanation: none. | |
| 146. | If during the execution of an instruction an exception is raised then |
| A. | the instruction is executed and the exception is handled |
| B. | the instruction is halted and the exception is handled |
| C. | the processor completes the execution and saves the data and then handle the exception |
| D. | none of the mentioned |
| Answer» B. the instruction is halted and the exception is handled | |
| Explanation: since the interrupt was raised during the execution of the instruction, the instruction cannot be executed and the exception is served immediately. | |
| 147. | is/are types of exceptions. |
| A. | trap |
| B. | interrupt |
| C. | system calls |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: none. | |
| 148. | The program used to find out errors is called |
| A. | debugger |
| B. | compiler |
| C. | assembler |
| D. | scanner |
| Answer» A. debugger | |
| Explanation: debugger is a program used to detect and correct errors in the program. | |
| 149. | The two facilities provided by the debugger is |
| A. | trace points |
| B. | break points |
| C. | compile |
| D. | both trace and break points |
| Answer» D. both trace and break points | |
| Explanation: the debugger provides us with the two facilities to improve the checking of errors. | |
| 151. | What are the different modes of operation of a computer? | |
| A. | user and system mode | |
| B. | user and supervisor mode | |
| C. | supervisor and trace mode | |
| D. | supervisor, user and trace mode | |
| Answer» B. user and supervisor mode | ||
| Explanation: the user programs are in the user mode and the system crucial programs are in the supervisor mode. | ||
| 152. | The instructions which can be run only supervisor mode are? |
| A. | non-privileged instructions |
| B. | system instructions |
| C. | privileged instructions |
| D. | exception instructions |
| Answer» C. privileged instructions | |
| Explanation: these instructions are those which can are crucial for the system’s performance and hence cannot be adultered by user programs, so is run only in supervisor mode. | |
| 153. | How is a privilege exception dealt with? |
| A. | the program is halted and the system switches into supervisor mode and restarts the program execution |
| B. | the program is stopped and removed from the queue |
| C. | the system switches the mode and starts the execution of a new process |
| D. | the system switches mode and runs the debugger |
| Answer» A. the program is halted and the system switches into supervisor mode and restarts the program execution | |
| Explanation: none. | |
| 154. | The DMA differs from the interrupt mode by |
| A. | the involvement of the processor for the operation |
| B. | the method of accessing the i/o devices |
| C. | the amount of data transfer possible |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| Explanation: dma is an approach of performing data transfers in bulk between memory and the external device without the intervention of the processor. | |
| 155. | The DMA transfers are performed by a control circuit called as |
| A. | device interface |
| B. | dma controller |
| C. | data controller |
| D. | overlooker |
| Answer» B. dma controller | |
| Explanation: the controller performs the functions that would normally be carried out by the processor. | |
| 156. | In DMA transfers, the required signals and addresses are given by the |
| A. | processor |
| B. | device drivers |
| C. | dma controllers |
| D. | the program itself |
| Answer» C. dma controllers | |
| Explanation: the dma controller acts as a processor for dma transfers and overlooks the entire process. | |
| 157. | After the completion of the DMA transfer, the processor is notified by |
| A. | acknowledge signal |
| B. | interrupt signal |
| C. | wmfc signal |
| D. | none of the mentioned |
| Answer» B. interrupt signal | |
| Explanation: the controller raises an interrupt signal to notify the processor that the transfer was complete. | |
| 158. | When the R/W bit of the status register of the DMA controller is set to 1. |
| A. | read operation is performed |
| B. | write operation is performed |
| C. | read & write operation is performed |
| D. | none of the mentioned |
| Answer» A. read operation is performed | |
| Explanation: none. | |
| 159. | The controller is connected to the |
| A. | processor bus |
| B. | system bus |
| C. | external bus |
| D. | none of the mentioned |
| Answer» B. system bus | |
| Explanation: the controller is directly connected to the system bus to provide faster transfer of data. | |
| 160. | Can a single DMA controller perform operations on two different disks simultaneously? |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the dma controller can perform operations on two different disks if the appropriate details are known. | |
| 161. | The technique whereby the DMA controller steals the access cycles of the processor to operate is called |
| A. | fast conning |
| B. | memory con |
| C. | cycle stealing |
| D. | memory stealing |
| Answer» C. cycle stealing | |
| Explanation: the controller takes over the processor’s access cycles and performs memory operations. | |
| 162. | The technique where the controller is given complete access to main memory is |
| A. | cycle stealing |
| B. | memory stealing |
| C. | memory con |
| D. | burst mode |
| Answer» D. burst mode | |
| Explanation: the controller is given full control of the memory access cycles and can transfer blocks at a faster rate. | |
| 163. | The controller uses to help with the transfers when handling network interfaces. |
| A. | input buffer storage |
| B. | signal enhancers |
| C. | bridge circuits |
| D. | all of the mentioned |
| Answer» A. input buffer storage | |
| Explanation: the controller stores the data to transfer in the buffer and then transfers it. | |
| 164. | To overcome the conflict over the possession of the BUS we use |
| A. | optimizers |
| B. | bus arbitrators |
| C. | multiple bus structure |
| D. | none of the mentioned |
| Answer» B. bus arbitrators | |
| Explanation: the bus arbitrator is used to overcome the contention over the bus possession. | |
| 165. | The registers of the controller are |
| A. | 64 bits |
| B. | 24 bits |
| C. | 32 bits |
| D. | 16 bits |
| Answer» C. 32 bits | |
| Explanation: none. | |
| 166. | When the process requests for a DMA transfer? |
| A. | then the process is temporarily suspended |
| B. | the process continues execution |
| C. | another process gets executed |
| D. | process is temporarily suspended & another process gets executed |
| Answer» D. process is temporarily suspended & another process gets executed | |
| Explanation: the process requesting the transfer is paused and the operation is performed, meanwhile another process is run on the processor. | |
| 167. | The DMA transfer is initiated by |
| A. | processor |
| B. | the process being executed |
| C. | i/o devices |
| D. | os |
| Answer» C. i/o devices | |
| Explanation: the transfer can only be initiated by an instruction of a program being executed. | |
| 168. | To resolve the clash over the access of the system BUS we use |
| A. | multiple bus |
| B. | bus arbitrator |
| C. | priority access |
| D. | none of the mentioned |
| Answer» B. bus arbitrator | |
| Explanation: the bus arbitrator is used to allow a device to access the bus based on certain parameters. | |
| 169. | The device which is allowed to initiate data transfers on the BUS at any time is called |
| A. | bus master |
| B. | processor |
| C. | bus arbitrator |
| D. | controller |
| Answer» A. bus master | |
| Explanation: the device which is currently accessing the bus is called as the bus master. | |
| 170. | BUS arbitration approach uses the involvement of the processor. |
| A. | centralised arbitration |
| B. | distributed arbitration |
| C. | random arbitration |
| D. | all of the mentioned |
| Answer» A. centralised arbitration | |
| Explanation: in this approach, the processor takes into account the various parameters and assigns the bus to that device. | |
| 171. | The circuit used for the request line is a |
| A. | open-collector |
| B. | ex-or circuit |
| C. | open-drain |
| D. | nand circuit |
| Answer» C. open-drain | |
| Explanation: none. | |
| 172. | The Centralised BUS arbitration is |
| A. | acknowledge signal |
| B. | bus grant signal |
| C. | response signal |
| D. | none of the mentioned |
| Answer» B. bus grant signal | |
| Explanation: the grant signal is passed from one device to the other until the device that has requested is found. | |
| 173. | Once the BUS is granted to a device |
| A. | it activates the bus busy line |
| B. | performs the required operation |
| C. | raises an interrupt |
| D. | all of the mentioned |
| Answer» A. it activates the bus busy line | |
| Explanation: the bus busy activated indicates that the bus is already allocated to a device and is being used. | |
| 174. | When the processor receives the request from a device, it responds by sending |
| A. | open-drain circuit |
| B. | open-collector circuit |
| C. | ex-or circuit |
| D. | nor circuit |
| Answer» B. open-collector circuit | |
| Explanation: none. | |
| 176. | The BUS busy line is used | |
| A. | to indicate the processor is busy | |
| B. | to indicate that the bus master is busy | |
| C. | to indicate the bus is already allocated | |
| D. | none of the mentioned | |
| Answer» C. to indicate the bus is already allocated | ||
| Explanation: none. | ||
| 177. | If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration. |
| A. | device a |
| B. | device b |
| C. | insufficient information |
| D. | none of the mentioned |
| Answer» B. device b | |
| Explanation: the device id’s of both the devices are passed on the lines and since the value of b is greater after the or operation it gets the bus. | |
| 178. | In Distributed arbitration, the device requesting the BUS |
| A. | asserts the start arbitration signal |
| B. | sends an interrupt signal |
| C. | sends an acknowledge signal |
| D. | none of the mentioned |
| Answer» A. asserts the start arbitration signal | |
| Explanation: none. | |
| 179. | How is a device selected in Distributed arbitration? |
| A. | to connect the various devices to the cpu |
| B. | to provide a path for communication between the processor and other devices |
| C. | to facilitate data transfer between various devices |
| D. | all of the mentioned |
| Answer» A. to connect the various devices to the cpu | |
| Explanation: the bus is used to allow the passage of commands and data between cpu and devices. | |
| 180. | The device which starts data transfer is called |
| A. | master |
| B. | transactor |
| C. | distributor |
| D. | initiator |
| Answer» D. initiator | |
| Explanation: the device which starts the data transfer is called an initiator. | |
| 181. | The device which interacts with the initiator is |
| A. | slave |
| B. | master |
| C. | responder |
| D. | friend |
| Answer» A. slave | |
| Explanation: the device which receives the commands from the initiator for data transfer. | |
| 182. | In synchronous BUS, the devices get the timing signals from |
| A. | timing generator in the device |
| B. | a common clock line |
| C. | timing signals are not used at all |
| D. | none of the mentioned |
| Answer» B. a common clock line | |
| Explanation: the devices receive their timing signals from the clock line of the bus. | |
| 183. | The delays caused in the switching of the timing signals is due to |
| A. | memory access time |
| B. | wmfc |
| C. | propagation delay |
| D. | processor delay |
| Answer» C. propagation delay | |
| Explanation: the time taken for the signal to reach the bus from the device or the circuit accounts for this delay. | |
| 184. | The time for which the data is to be on the BUS is affected by |
| A. | propagation delay of the circuit |
| B. | setup time of the device |
| C. | memory access time |
| D. | propagation delay of the circuit & setup time of the device |
| Answer» D. propagation delay of the circuit & setup time of the device | |
| Explanation: the time for which the data is held is larger than the time taken for propagation delay and setup time. | |
| 185. | The Master strobes the slave at the end of each clock cycle in Synchronous BUS. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 186. | Which is fed into the BUS first by the initiator? |
| A. | data |
| B. | address |
| C. | commands or controls |
| D. | address, commands or controls |
| Answer» D. address, commands or controls | |
| Explanation: none. | |
| 187. | The devices with variable speeds are usually connected using asynchronous BUS. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the devices with variable speeds are connected using asynchronous bus, as the devices share a master-slave relationship. | |
| 188. | The MSYN signal is initiated |
| A. | soon after the address and commands are loaded |
| B. | soon after the decoding of the address |
| C. | after the slave gets the commands |
| D. | none of the mentioned |
| Answer» B. soon after the decoding of the address | |
| Explanation: this signal is activated by the master to tell the slave that the required commands are on the bus. | |
| 189. | In IBM’s S360/370 systems lines are used to select the I/O devices. |
| A. | scan in and out |
| B. | connect |
| C. | search |
| D. | peripheral |
| Answer» A. scan in and out | |
| Explanation: the signal is used to scan and connect to input or output devices. | |
| 190. | The meter in and out lines are used for |
| A. | monitoring the usage of devices |
| B. | monitoring the amount of data transferred |
| C. | measure the cpu usage |
| D. | none of the mentioned |
| Answer» A. monitoring the usage of devices | |
| Explanation: the line is used to monitor the usage of the device for a process. | |
| 191. | MRDC stands for |
| A. | memory read enable |
| B. | memory ready command |
| C. | memory re-direct command |
| D. | none of the mentioned |
| Answer» B. memory ready command | |
| Explanation: the command is used to initiate a read from memory operation. | |
| 192. | The BUS that allows I/O, memory and Processor to coexist is |
| A. | attributed bus |
| B. | processor bus |
| C. | backplane bus |
| D. | external bus |
| Answer» C. backplane bus | |
| Explanation: none. | |
| 193. | The transmission on the asynchronous BUS is also called |
| A. | switch mode transmission |
| B. | variable transfer |
| C. | bulk transfer |
| D. | hand-shake transmission |
| Answer» D. hand-shake transmission | |
| Explanation: the asynchronous transmission is termed as hand-shake transfer because the master intimates the slave after each step of the transfer. | |
| 194. | Asynchronous mode of transmission is suitable for systems with multiple peripheral devices. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this mode of transmission is suitable for multiple device situation as it supports variable speed transfer. | |
| 195. | The asynchronous BUS mode of transmission allows for a faster mode of data transfer. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: none. | |
| 196. | serves as an intermediary between the device and the BUSes. |
| A. | interface circuits |
| B. | device drivers |
| C. | buffers |
| D. | none of the mentioned |
| Answer» A. interface circuits | |
| Explanation: the interface circuits act as a hardware interface between the device and the software side. | |
| 197. | The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is |
| A. | bus side |
| B. | port side |
| C. | hardwell side |
| D. | software side |
| Answer» B. port side | |
| Explanation: this side connects the device to the motherboard. | |
| 198. | What is the interface circuit? |
| A. | helps in installing of the software driver for the device |
| B. | houses the buffer that helps in data transfer |
| C. | helps in the decoding of the address on the address bus |
| D. | none of the mentioned |
| Answer» C. helps in the decoding of the address on the address bus | |
| Explanation: once the address is put on the bus the interface circuit decodes the address and uses the buffer space to transfer data. | |
| 199. | The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: by doing this the interface circuits provide a better interconnection between devices. | |
| 200. | The Interface circuits generate the appropriate timing signals required by the BUS control scheme. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the interface circuits generate the required clock signal for the synchronous mode of transfer. | |
| 201. | The status flags required for data transfer is present in |
| A. | device |
| B. | device driver |
| C. | interface circuit |
| D. | none of the mentioned |
| Answer» C. interface circuit | |
| Explanation: the circuit holds the flags which are required for data transfers. | |
| 202. | User programmable terminals that combine VDT hardware with built-in microprocessor is |
| A. | kips |
| B. | pc |
| C. | mainframe |
| D. | intelligent terminals |
| Answer» D. intelligent terminals | |
| Explanation: none. | |
| 203. | Which most popular input device is used today for interactive processing and for the one line entry of data for batch processing? |
| A. | mouse |
| B. | magnetic disk |
| C. | visual display terminal |
| D. | card punch |
| Answer» A. mouse | |
| Explanation: in batch processing systems the processes are grouped into batches and they’re executed in batches. | |
| 204. | is used as an intermediate to extend the processor BUS. |
| A. | bridge |
| B. | router |
| C. | connector |
| D. | gateway |
| Answer» A. bridge | |
| Explanation: the bridge circuit is basically used to extend the processor bus to connect devices. | |
| 205. | is an extension of the processor BUS. |
| A. | scsi bus |
| B. | usb |
| C. | pci bus |
| D. | none of the mentioned |
| Answer» C. pci bus | |
| Explanation: the pci bus is used as an extension of the processor bus and devices connected to it, is like connected to the processor itself. | |
| 206. | What is the full form of ISA? |
| A. | international american standard |
| B. | industry standard architecture |
| C. | international standard architecture |
| D. | none of the mentioned |
| Answer» B. industry standard architecture | |
| Explanation: the isa is an architectural standard developed by ibm for its pc’s. | |
| 207. | What is the full form of ANSI? |
| A. | american national standards institute |
| B. | architectural national standards institute |
| C. | asian national standards institute |
| D. | none of the mentioned |
| Answer» A. american national standards institute | |
| Explanation: the ansi is one of the standard architecture used by companies in designing the systems. | |
| 208. | SCSI stands for |
| A. | signal computer system interface |
| B. | small computer system interface |
| C. | small coding system interface |
| D. | signal coding system interface |
| Answer» B. small computer system interface view more info and meaning of SCSI | |
| Explanation: the scsi bus is used to connect disks and video controllers. | |
| 209. | ISO stands for |
| A. | international standards organisation |
| B. | international software organisation |
| C. | industrial standards organisation |
| D. | industrial software organisation |
| Answer» A. international standards organisation view more info and meaning of ISO | |
| Explanation: the iso is yet another architectural standard, used to design systems. | |
| 210. | The system developed by IBM with ISA architecture is |
| A. | sparc |
| B. | sun-sparc |
| C. | pc-at |
| D. | none of the mentioned |
| Answer» C. pc-at | |
| Explanation: none. | |
| 211. | IDE disk is connected to the PCI BUS using interface. |
| A. | isa |
| B. | iso |
| C. | ansi |
| D. | ieee |
| Answer» A. isa | |
| Explanation: none. | |
| 212. | IDE stands for |
| A. | integrated device electronics |
| B. | international device encoding |
| C. | industrial decoder electronics |
| D. | international decoder encoder |
| Answer» A. integrated device electronics view more info and meaning of IDE | |
| Explanation: the ide interface is used to connect the hard disk to the processor in most of the pentium processors. | |
| 213. | The circuit enables the generation of the ASCII code when the key is pressed. |
| A. | generator |
| B. | debouncing |
| C. | encoder |
| D. | logger |
| Answer» C. encoder | |
| Explanation: the signal generated upon the pressing of a button is encoded by the encoder circuit into the corresponding ascii value. | |
| 214. | To overcome multiple signals being generated upon a single press of the button, we make use of |
| A. | generator circuit |
| B. | debouncing circuit |
| C. | multiplexer |
| D. | xor circuit |
| Answer» B. debouncing circuit | |
| Explanation: when the button is pressed, the contact surfaces bounce and hence it might lead to the generation of multiple signals. in order to overcome this, we use debouncing circuits. | |
| 215. | The best mode of connection between devices which need to send or receive large amounts of data over a short distance is |
| A. | bus |
| B. | serial port |
| C. | parallel port |
| D. | isochronous port |
| Answer» C. parallel port | |
| Explanation: the parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence increasing transfer rates. | |
| 216. | The output of the encoder circuit is/are |
| A. | ascii code |
| B. | ascii code and the valid signal |
| C. | encoded signal |
| D. | none of the mentioned |
| Answer» B. ascii code and the valid signal | |
| Explanation: the encoder outputs the ascii value along with the valid signal which indicates that a key was pressed. | |
| 217. | The disadvantage of using a parallel mode of communication is |
| A. | it is costly |
| B. | leads to erroneous data transfer |
| C. | security of data |
| D. | all of the mentioned |
| Answer» A. it is costly | |
| Explanation: the parallel mode of data transfer is costly as it involves data being sent over parallel lines. | |
| 218. | In a 32 bit processor, the A0 bit of the address line is connected to of the parallel port interface. |
| A. | valid bit |
| B. | idle bit |
| C. | interrupt enable bit |
| D. | status or data register |
| Answer» D. status or data register | |
| Explanation: none. | |
| 219. | The Status flag circuit is implemented using |
| A. | rs flip flop |
| B. | d flip flop |
| C. | jk flip flop |
| D. | xor circuit |
| Answer» B. d flip flop | |
| Explanation: the circuit is implemented using the edge triggered d flip flop, that | |
| 220. | In the output interface of the parallel port, along with the valid signal is also sent. |
| A. | data |
| B. | idle signal |
| C. | interrupt |
| D. | acknowledge signal |
| Answer» B. idle signal | |
| Explanation: the idle signal is used to check if the device is idle and ready to receive data. | |
| 221. | DDR stands for |
| A. | data direction register |
| B. | data decoding register |
| C. | data decoding rate |
| D. | none of the mentioned |
| Answer» A. data direction register | |
| Explanation: this register is used to control the flow of data from the dataout register. | |
| 222. | In a general 8-bit parallel interface, the INTR line is connected to |
| A. | status and control unit |
| B. | ddr |
| C. | register select |
| D. | none of the mentioned |
| Answer» A. status and control unit | |
| Explanation: none. | |
| 223. | The mode of transmission of data, where one bit is sent for each clock cycle is |
| A. | asynchronous |
| B. | parallel |
| C. | serial |
| D. | isochronous |
| Answer» D. isochronous | |
| Explanation: in the isochronous mode of transmission, each bit of the data is sent per each cycle. | |
| 224. | The transformation between the Parallel and serial ports is done with the help of |
| A. | flip flops |
| B. | logic circuits |
| C. | shift registers |
| D. | none of the mentioned |
| Answer» C. shift registers | |
| Explanation: the shift registers are used to output the data in the desired format based on the need. | |
| 226. | The double buffer is used for | |
| A. | enabling retrieval of multiple bits of input | |
| B. | combining the input and output operations | |
| C. | extending the buffer capacity | |
| D. | none of the mentioned | |
| Answer» A. enabling retrieval of multiple bits of input | ||
| Explanation: none. | ||
| 227. | UART stands for |
| A. | universal asynchronous relay transmission |
| B. | universal accumulator register transfer |
| C. | universal asynchronous receiver transmitter |
| D. | none of the mentioned |
| Answer» C. universal asynchronous receiver transmitter | |
| Explanation: the uart is a standard developed for designing serial ports. | |
| 228. | The key feature of UART is |
| A. | its architectural design |
| B. | its simple implementation |
| C. | its general purpose usage |
| D. | its enhancement of connecting low speed devices |
| Answer» D. its enhancement of connecting low speed devices | |
| Explanation: none. | |
| 229. | The data transfer in UART is done in |
| A. | asynchronous start stop format |
| B. | synchronous start stop format |
| C. | isochronous format |
| D. | ebdic format |
| Answer» A. asynchronous start stop format | |
| Explanation: this basically means that the data transfer is done in asynchronous mode. | |
| 230. | The standard used in serial ports to facilitate communication is |
| A. | rs-246 |
| B. | rs-lnk |
| C. | rs-232-c |
| D. | both rs-246 and rs-lnk |
| Answer» C. rs-232-c | |
| Explanation: this is a standard that acts as a protocol for message communication involving serial ports. | |
| 231. | In a serial port interface, the INTR line is connected to |
| A. | status register |
| B. | shift register |
| C. | chip select |
| D. | none of the mentioned |
| Answer» A. status register | |
| Explanation: none. | |
| 232. | The PCI follows a set of standards primarily used in PC’s. |
| A. | intel |
| B. | motorola |
| C. | ibm |
| D. | sun |
| Answer» C. ibm | |
| Explanation: the pci bus has a closer resemblance to ibm architecture. | |
| 233. | The is the BUS used in Macintosh PC’s. |
| A. | nubus |
| B. | eisa |
| C. | pci |
| D. | none of the mentioned |
| Answer» A. nubus | |
| Explanation: the nubus is an extension of the processor bus in macintosh pc’s. | |
| 234. | The key feature of the PCI BUS is |
| A. | low cost connectivity |
| B. | plug and play capability |
| C. | expansion of bandwidth |
| D. | none of the mentioned |
| Answer» B. plug and play capability | |
| Explanation: the pci bus was the first to introduce plug and play interface for i/o devices. | |
| 235. | PCI stands for |
| A. | peripheral component interconnect |
| B. | peripheral computer internet |
| C. | processor computer interconnect |
| D. | processor cable interconnect |
| Answer» A. peripheral component interconnect | |
| Explanation: the pci bus is used as an extension for the processor bus. | |
| 236. | The PCI BUS supports address space/s. |
| A. | i/o |
| B. | memory |
| C. | configuration |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the pci bus is mainly built to provide a wide range of connectivity for devices. | |
| 237. | address space gives the PCI its plug and plays capability. |
| A. | configuration |
| B. | i/o |
| C. | memory |
| D. | all of the mentioned |
| Answer» A. configuration | |
| Explanation: the configuration address space is used to store the details of the connected device. | |
| 238. | provides a separate physical connection to the memory. |
| A. | pci bus |
| B. | pci interface |
| C. | pci bridge |
| D. | switch circuit |
| Answer» C. pci bridge | |
| Explanation: the pci bridge is a circuit that acts as a bridge between the bus and the memory. | |
| 239. | When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the address is stored by the slave in a buffer and hence it is not required by the master to hold it. | |
| 240. | The master is also called as in PCI terminology. |
| A. | initiator |
| B. | commander |
| C. | chief |
| D. | starter |
| Answer» A. initiator | |
| Explanation: the master is also called as an initiator in pci terminology as it is the one that initiates a data transfer. | |
| 241. | Signals whose names end in are asserted in the low voltage state. |
| A. | $ |
| B. | # |
| C. | * |
| D. | ! |
| Answer» B. # | |
| Explanation: none. | |
| 242. | A complete transfer operation over the BUS, involving the address and a burst of data is called |
| A. | transaction |
| B. | transfer |
| C. | move |
| D. | procedure |
| Answer» A. transaction | |
| Explanation: none. | |
| 243. | The device connected to the BUS are given addresses of bit. |
| A. | 24 |
| B. | 64 |
| C. | 32 |
| D. | 16 |
| Answer» B. 64 | |
| Explanation: each of the devices connected to the bus will be allocated an address during the initialization phase. | |
| 244. | The PCI BUS has interrupt request lines. |
| A. | 6 |
| B. | 1 |
| C. | 4 |
| D. | 3 |
| Answer» C. 4 | |
| Explanation: the interrupt request lines are used by the devices connected to raise the interrupts. | |
| 245. | signal is sent by the initiator to indicate the duration of the transaction. |
| A. | frame# |
| B. | irdy# |
| C. | tmy# |
| D. | seld# |
| Answer» A. frame# | |
| Explanation: the frame signal is used | |
| 246. | signal is used to enable commands. |
| A. | frame# |
| B. | irdy# |
| C. | tmy# |
| D. | c/be# |
| Answer» D. c/be# | |
| Explanation: the signal is used to enable 4 command lines. | |
| 247. | IRDY# signal is used for |
| A. | selecting the interrupt line |
| B. | sending an interrupt |
| C. | saying that the initiator is ready |
| D. | none of the mentioned |
| Answer» C. saying that the initiator is ready | |
| Explanation: the initiator transmits this signal to tell the target that it is ready. | |
| 248. | The signal used to indicate that the slave is ready is |
| A. | slry# |
| B. | trdy# |
| C. | dsdy# |
| D. | none of the mentioned |
| Answer» B. trdy# | |
| Explanation: none. | |
| 249. | DEVSEL# signal is used |
| A. | to select the device |
| B. | to list all the devices connected |
| C. | by the device to indicate that it is ready for a transaction |
| D. | none of the mentioned |
| Answer» C. by the device to indicate that it is ready for a transaction | |
| Explanation: this is signal is activated by the device after it as recognized the address and commands put on the bus. | |
| 251. | The key features of the SCSI BUS are | |
| A. | the cost effective connective media | |
| B. | the ability overlap data transfer requests | |
| C. | the highly efficient data transmission | |
| D. | none of the mentioned | |
| Answer» B. the ability overlap data transfer requests | ||
| Explanation: the scsi bus can overlap various data transfer requests by the devices. | ||
| 252. | In a data transfer operation involving SCSI BUS, the control is with |
| A. | initiator |
| B. | target |
| C. | scsi controller |
| D. | target controller |
| Answer» D. target controller | |
| Explanation: the initiator involves in the arbitration process and after winning the bus it’ll hand over the control to the target controller. | |
| 253. | In SCSI transfers the processor is not aware of the data being transferred. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the processor or the controller is unaware of the data being transferred. | |
| 254. | What is DB(P) line? |
| A. | that the data line is carrying the device information |
| B. | that the data line is carrying the parity information |
| C. | that the data line is partly closed |
| D. | that the data line is temporarily occupied |
| Answer» B. that the data line is carrying the parity information | |
| Explanation: none. | |
| 255. | The BSY signal signifies |
| A. | the bus is busy |
| B. | the controller is busy |
| C. | the initiator is busy |
| D. | the target is busy |
| Answer» A. the bus is busy | |
| Explanation: this signal is generally initiated when the bus is currently occupied in an operation. | |
| 256. | The SEL signal signifies |
| A. | the initiator is selected |
| B. | the device for bus control is selected |
| C. | that the target is being selected |
| D. | none of the mentioned |
| Answer» B. the device for bus control is selected | |
| Explanation: this signal is usually asserted during the selection or reselection process. | |
| 257. | signal is asserted when the initiator wishes to send a message to the target. |
| A. | msg |
| B. | app |
| C. | sms |
| D. | atn |
| Answer» D. atn | |
| Explanation: the atn signal is short for attention, which is used to intimate the target that the initiator sent a message to it. | |
| 258. | The MSG signal is used |
| A. | to send a message to the target |
| B. | to receive a message from the mailbox |
| C. | to tell that the information being sent is a message |
| D. | none of the mentioned |
| Answer» C. to tell that the information being sent is a message | |
| Explanation: none. | |
| 259. | is used to reset all the device controls to their startup state. |
| A. | srt |
| B. | rst |
| C. | atn |
| D. | none of the mentioned |
| Answer» B. rst | |
| Explanation: none. | |
| 260. | SCSI stands for |
| A. | small computer system interface |
| B. | switch computer system interface |
| C. | small component system interface |
| D. | none of the mentioned |
| Answer» A. small computer system interface view more info and meaning of SCSI | |
| Explanation: the scsi bus is one of the expansion buses used in a system. | |
| 261. | ANSI stands for |
| A. | american national system interface |
| B. | ascii national standard interface |
| C. | american network system interface |
| D. | american national standard institute |
| Answer» D. american national standard institute view more info and meaning of ANSI | |
| Explanation: this a standard for designing buses and other system components. | |
| 262. | A narrow SCSI BUS has data lines. |
| A. | 6 |
| B. | 8 |
| C. | 16 |
| D. | 4 |
| Answer» B. 8 | |
| Explanation: the scsi bus which is narrow is capable of transferring 8 bits of data at a time. | |
| 263. | HVD stands for |
| A. | high voltage differential |
| B. | high voltage density |
| C. | high video definition |
| D. | none of the mentioned |
| Answer» A. high voltage differential | |
| Explanation: this is a type of signaling which uses 5v of current. | |
| 264. | For better transfer rates on the SCSI BUS the length of the cable is limited to |
| A. | 2m |
| B. | 4m |
| C. | 1.3m |
| D. | 1.6m |
| Answer» D. 1.6m | |
| Explanation: to increase the transmission rate in scsi in se mode of transfer the wire length is restricted to 1.6m. | |
| 265. | The mode of data transfer used by the controller is |
| A. | interrupt |
| B. | dma |
| C. | asynchronous |
| D. | synchronous |
| Answer» B. dma | |
| Explanation: none. | |
| 266. | The data is stored on the disk in the form of blocks called |
| A. | pages |
| B. | frames |
| C. | sectors |
| D. | tables |
| Answer» C. sectors | |
| Explanation: the data is stored on the disk in the form of a collection of blocks called as sectors. | |
| 267. | The high speed mode of operation of the USB was introduced by |
| A. | isa |
| B. | usb 3.0 |
| C. | usb 2.0 |
| D. | ansi |
| Answer» C. usb 2.0 | |
| Explanation: the high-speed mode of operation was introduced with usb 2.0, which enabled the usb to operate at 480 mb/s. | |
| 268. | The sampling process in speaker output is a process. |
| A. | asynchronous |
| B. | synchronous |
| C. | isochronous |
| D. | none of the mentioned |
| Answer» C. isochronous | |
| Explanation: the isochronous process means each bit of data is separated by a time interval. | |
| 269. | The I/O devices form the of the tree structure. |
| A. | leaves |
| B. | subordinate roots |
| C. | left subtrees |
| D. | right subtrees |
| Answer» A. leaves | |
| Explanation: the i/o devices form the leaves of the structure. | |
| 270. | USB is a parallel mode of transmission of data and this enables for the fast speeds of data transfers. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the usb does a serial mode of data transfer. | |
| 271. | In USB the devices can communicate with each other. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: it allows only the host to communicate with the devices and not between themselves. | |
| 272. | The device can send a message to the host by taking part in for the communication path. |
| A. | arbitration |
| B. | polling |
| C. | prioritizing |
| D. | none of the mentioned |
| Answer» B. polling | |
| Explanation: none. | |
| 273. | When the USB is connected to a system, its root hub is connected to the |
| A. | pci bus |
| B. | scsi bus |
| C. | processor bus |
| D. | ide |
| Answer» C. processor bus | |
| Explanation: the usb’s root is connected to the processor directly using the bus. | |
| 274. | The devices connected to USB is assigned a address. |
| A. | 9 bit |
| B. | 16 bit |
| C. | 4 bit |
| D. | 7 bit |
| Answer» D. 7 bit | |
| Explanation: to make it easier for recognition the devices are given 7 bit addresses. | |
| 276. | Locations in the device to or from which data transfers can take place is called |
| A. | end points |
| B. | hosts |
| C. | source |
| D. | none of the mentioned |
| Answer» A. end points | |
| Explanation: none. | |
| 277. | A USB pipe is a channel. |
| A. | simplex |
| B. | half-duplex |
| C. | full-duplex |
| D. | both simplex and full-duplex |
| Answer» C. full-duplex | |
| Explanation: this means that the pipe is bi-directional in sending messages or information. | |
| 278. | The type/s of packets sent by the USB is/are |
| A. | data |
| B. | address |
| C. | control |
| D. | both data and control |
| Answer» D. both data and control | |
| Explanation: this means that the usb gets both data and control signals required for the transfer operation. | |
| 279. | The first field of any packet is |
| A. | pid |
| B. | addr |
| C. | endp |
| D. | crc16 |
| Answer» A. pid | |
| Explanation: the pid is the field that is used to identify the device (the device id). | |
| 280. | The 4 bit PID’s are transmitted twice. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the fields are transmitted twice, once with the true values and the second time with the complemented values. | |
| 281. | The last field in the packet is |
| A. | pid |
| B. | addr |
| C. | endp |
| D. | crc |
| Answer» D. crc | |
| Explanation: the last 5 bits of the packet is used for error checking, that is cyclic redundancy check. | |
| 282. | The CRC bits are computed based on the values of the |
| A. | pid |
| B. | addr |
| C. | endp |
| D. | both addr and endp |
| Answer» D. both addr and endp | |
| Explanation: the crc bits are calculated based on the values of the address and endp. | |
| 283. | The data packets can contain data upto |
| A. | 512 bytes |
| B. | 256 bytes |
| C. | 1024 bytes |
| D. | 2 kb |
| Answer» C. 1024 bytes | |
| Explanation: none. | |
| 284. | The signal is used to indicate the beginning of a new frame. |
| A. | start |
| B. | sof |
| C. | beg |
| D. | none of the mentioned |
| Answer» B. sof | |
| Explanation: the sof(state of frame) is used to indicate the beginning of a new frame. | |
| 285. | The SOF is transmitted every |
| A. | 1s |
| B. | 5s |
| C. | 1ms |
| D. | 1us |
| Answer» C. 1ms | |
| Explanation: none. | |
| 286. | The logic operations are simpler to implement using logic circuits. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the logic operation includes and, or, xor etc. | |
| 287. | The logic operations are implemented using circuits. |
| A. | bridge |
| B. | logical |
| C. | combinatorial |
| D. | gate |
| Answer» C. combinatorial | |
| Explanation: the combinatorial circuits means, using the basic universal gates. | |
| 288. | In full adders the sum circuit is implemented using |
| A. | and & or gates |
| B. | nand gate |
| C. | xor |
| D. | xnor |
| Answer» C. xor | |
| Explanation: sum = a ^ b ^ c (‘^’ indicates xor operation). | |
| 289. | The usual implementation of the carry circuit involves |
| A. | and & or gates |
| B. | xor |
| C. | nand |
| D. | xnor |
| Answer» B. xor | |
| Explanation: in case of full and half adders this method is used. | |
| 290. | A gate is used to detect the occurrence of an overflow. |
| A. | nand |
| B. | xor |
| C. | xnor |
| D. | and |
| Answer» B. xor | |
| Explanation: the overflow is detected by cn^cn-1 (‘^’ indicates xor operation). | |
| 291. | The delay reduced to in the carry look ahead adder is |
| A. | 5 |
| B. | 8 |
| C. | 10 |
| D. | 2n |
| Answer» A. 5 | |
| Explanation: none. | |
| 292. | The product of 1101 & 1011 is |
| A. | 10001111 |
| B. | 10101010 |
| C. | 11110000 |
| D. | 11001100 |
| Answer» A. 10001111 | |
| Explanation: the above operation is performed using binary multiplication. | |
| 293. | The is used to coordinate the operation of the multiplier. |
| A. | controller |
| B. | coordinator |
| C. | control sequencer |
| D. | none of the mentioned |
| Answer» C. control sequencer | |
| Explanation: this performs the required sequencing of the various parts of the circuit. | |
| 294. | The multiplicand and the control signals are passed through to the n-bit adder via |
| A. | mux |
| B. | demux |
| C. | encoder |
| D. | decoder |
| Answer» A. mux | |
| Explanation: none. | |
| 295. | The method used to reduce the maximum number of summands by half is |
| A. | fast multiplication |
| B. | bit-pair recording |
| C. | quick multiplication |
| D. | none of the mentioned |
| Answer» B. bit-pair recording | |
| Explanation: it reduces the number of summands by concatenating them. | |
| 296. | The multiplier -6(11010) is recorded as |
| A. | 0-1-2 |
| B. | 0-1+1-10 |
| C. | -2-10 |
| D. | none of the mentioned |
| Answer» A. 0-1-2 | |
| Explanation: none. | |
| 297. | CSA stands for? |
| A. | computer speed addition |
| B. | carry save addition |
| C. | computer service architecture |
| D. | none of the mentioned |
| Answer» A. computer speed addition | |
| Explanation: the csa is used to speed up the addition of multiplicands. | |
| 298. | The decimal numbers represented in the computer are called as floating point numbers, as the decimal point floats through the number. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: by doing this the computer is capable of accommodating the large float numbers also. | |
| 299. | The numbers written to the power of 10 in the representation of decimal numbers are called as |
| A. | height factors |
| B. | size factors |
| C. | scale factors |
| D. | none of the mentioned |
| Answer» C. scale factors | |
| Explanation: these are called as scale factors cause they’re responsible in determining the degree of specification of a number. | |
| 301. | constitute the representation of the floating number. |
| A. | sign |
| B. | significant digits |
| C. | scale factor |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the following factors are responsible for the representation of the number. | |
| 302. | The sign followed by the string of digits is called as |
| A. | significant |
| B. | determinant |
| C. | mantissa |
| D. | exponent |
| Answer» C. mantissa | |
| Explanation: the mantissa also consists of the decimal point. | |
| 303. | The normalized representation of 0.0010110 * 2 9 is |
| A. | 0 10001000 0010110 |
| B. | 0 10000101 0110 |
| C. | 0 10101010 1110 |
| D. | 0 11110100 11100 |
| Answer» B. 0 10000101 0110 | |
| Explanation: normalized representation is done by shifting the decimal point. | |
| 304. | The 32 bit representation of the decimal number is called as |
| A. | double-precision |
| B. | single-precision |
| C. | extended format |
| D. | none of the mentioned |
| Answer» B. single-precision | |
| Explanation: none. | |
| 305. | In 32 bit representation the scale factor as a range of |
| A. | -128 to 127 |
| B. | -256 to 255 |
| C. | 0 to 255 |
| D. | none of the mentioned |
| Answer» A. -128 to 127 | |
| Explanation: since the exponent field has only 8 bits to store the value. | |
| 306. | In double precision format, the size of the mantissa is |
| A. | 32 bit |
| B. | 52 bit |
| C. | 64 bit |
| D. | 72 bit |
| Answer» B. 52 bit | |
| Explanation: the double precision format is also called as 64 bit representation. | |
| 307. | have been developed specifically for pipelined systems. |
| A. | utility software |
| B. | speed up utilities |
| C. | optimizing compilers |
| D. | none of the mentioned |
| Answer» C. optimizing compilers | |
| Explanation: the compilers which are designed to remove redundant parts of the code are called as optimizing compilers. | |
| 308. | The pipelining process is also called as |
| A. | superscalar operation |
| B. | assembly line operation |
| C. | von neumann cycle |
| D. | none of the mentioned |
| Answer» B. assembly line operation | |
| Explanation: it is called so because it performs its operation at the assembly level. | |
| 309. | To increase the speed of memory access in pipelining, we make use of |
| A. | modification in processor architecture |
| B. | clock |
| C. | special unit |
| D. | control unit |
| Answer» B. clock | |
| Explanation: the time cycle of the clock is adjusted to perform the interleaving. | |
| 310. | Each stage in pipelining should be completed within cycle. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» A. 1 | |
| Explanation: the stages in the pipelining should get completed within one cycle to increase the speed of performance. | |
| 311. | In pipelining the task which requires the least time is performed first. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: this is done to avoid starvation of the longer task. | |
| 312. | If a unit completes its task before the allotted time period, then |
| A. | special memory locations |
| B. | special purpose registers |
| C. | cache |
| D. | buffers |
| Answer» C. cache | |
| Explanation: by using the cache we can reduce the speed of memory access by a factor of 10. | |
| 313. | The periods of time when the unit is idle is called as |
| A. | stalls |
| B. | bubbles |
| C. | hazards |
| D. | both stalls and bubbles |
| Answer» D. both stalls and bubbles | |
| Explanation: the stalls are a type of hazards that affect a pipelined system. | |
| 314. | The throughput of a super scalar processor is |
| A. | less than 1 |
| B. | 1 |
| C. | more than 1 |
| D. | not known |
| Answer» C. more than 1 | |
| Explanation: the throughput of a processor is measured by using the number of instructions executed per second. | |
| 315. | When the processor executes multiple instructions at a time it is said to use |
| A. | single issue |
| B. | multiplicity |
| C. | visualization |
| D. | multiple issues |
| Answer» D. multiple issues | |
| Explanation: none. | |
| 316. | The plays a very vital role in case of super scalar processors. |
| A. | compilers |
| B. | motherboard |
| C. | memory |
| D. | peripherals |
| Answer» A. compilers | |
| Explanation: the compilers are programmed to arrange the instructions to get more throughput. | |
| 317. | If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have |
| A. | exception handling |
| B. | imprecise exceptions |
| C. | error correction |
| D. | none of the mentioned |
| Answer» B. imprecise exceptions | |
| Explanation: the processor since as executed the following instructions even though an exception was raised, hence the exception is treated as imprecise. | |
| 318. | In super-scalar mode, all the similar instructions are grouped and executed together. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the instructions are grouped meaning that the instructions fetch and decode and other cycles are overlapped. | |
| 319. | Since it uses the out of order mode of execution, the results are stored in |
| A. | buffers |
| B. | special memory locations |
| C. | temporary registers |
| D. | tlb |
| Answer» C. temporary registers | |
| Explanation: the results are stored in temporary locations and are arranged afterward. | |
| 320. | The step where in the results stored in the temporary register is transferred into the permanent register is called as |
| A. | final step |
| B. | commitment step |
| C. | last step |
| D. | inception step |
| Answer» B. commitment step | |
| Explanation: none. | |
| 321. | A special unit used to govern the out of order execution of the instructions is called as |
| A. | commitment unit |
| B. | temporal unit |
| C. | monitor |
| D. | supervisory unit |
| Answer» A. commitment unit | |
| Explanation: this unit monitors the execution of the instructions and makes sure that the final result is in order. | |
| 322. | The commitment unit uses a queue called |
| A. | record buffer |
| B. | commitment buffer |
| C. | storage buffer |
| D. | none of the mentioned |
| Answer» A. record buffer | |
| Explanation: none. | |
| 323. | The CISC stands for |
| A. | computer instruction set compliment |
| B. | complete instruction set compliment |
| C. | computer indexed set components |
| D. | complex instruction set computer |
| Answer» D. complex instruction set computer view more info and meaning of CISC | |
| Explanation: cisc is a computer architecture where in the processor performs more complex operations in one step. | |
| 324. | The computer architecture aimed at reducing the time of execution of instructions is |
| A. | cisc |
| B. | risc |
| C. | isa |
| D. | anna |
| Answer» B. risc | |
| Explanation: the risc stands for reduced instruction set computer. | |
| 326. | The RISC processor has a more complicated design than CISC. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the risc processor design is more simpler than cisc and it consists of fewer transistors. | |
| 327. | The iconic feature of the RISC machine among the following is |
| A. | reduced number of addressing modes |
| B. | increased memory size |
| C. | having a branch delay slot |
| D. | all of the mentioned |
| Answer» C. having a branch delay slot | |
| Explanation: a branch delay slot is an instruction space immediately following a jump or branch. | |
| 328. | Both the CISC and RISC architectures have been developed to reduce the |
| A. | cost |
| B. | time delay |
| C. | semantic gap |
| D. | all of the mentioned |
| Answer» C. semantic gap | |
| Explanation: the semantic gap is the gap between the high level language and the low level language. | |
| 329. | Pipe-lining is a unique feature of |
| A. | risc |
| B. | cisc |
| C. | isa |
| D. | iana |
| Answer» A. risc | |
| Explanation: the risc machine architecture was the first to implement pipe-lining. | |
| 330. | In CISC architecture most of the complex instructions are stored in |
| A. | register |
| B. | diodes |
| C. | cmos |
| D. | transistors |
| Answer» D. transistors | |
| Explanation: in cisc architecture more emphasis is given on the instruction set | |
| 331. | Which of the architecture is power efficient? |
| A. | cisc |
| B. | risc |
| C. | isa |
| D. | iana |
| Answer» B. risc | |
| Explanation: hence the risc architecture is followed in the design of mobile devices. | |
| 332. | For converting a virtual address into the physical address, the programs are divided into |
| A. | pages |
| B. | frames |
| C. | segments |
| D. | blocks |
| Answer» A. pages | |
| Explanation: on the physical memory side the memory is divided into pages. | |
| 333. | The memory allocated to each page is contiguous. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: each page might be allocated memory deferentially but the memory for one page will be continuous. | |
| 334. | The pages size shouldn’t be too small, as this would lead to |
| A. | transfer errors |
| B. | increase in operation time |
| C. | increase in access time |
| D. | decrease in performance |
| Answer» C. increase in access time | |
| Explanation: the access time of the magnetic disk is much longer than the access time of the memory. | |
| 335. | The cache bridges the speed gap between and |
| A. | ram and rom |
| B. | ram and secondary memory |
| C. | processor and ram |
| D. | none of the mentioned |
| Answer» C. processor and ram | |
| Explanation: the cache is a hardware implementation to reduce the access time for processor operations. | |
| 336. | The virtual memory bridges the size and speed gap between and |
| A. | ram and rom |
| B. | ram and secondary memory |
| C. | processor and ram |
| D. | none of the mentioned |
| Answer» B. ram and secondary memory | |
| Explanation: the virtual memory basically works as an extension of the ram. | |
| 337. | The higher order bits of the virtual address generated by the processor forms the |
| A. | table number |
| B. | frame number |
| C. | list number |
| D. | page number |
| Answer» D. page number | |
| Explanation: the higher order bits indicate the page number which points | |
| 338. | The page length shouldn’t be too long because |
| A. | it reduces the program efficiency |
| B. | it increases the access time |
| C. | it leads to wastage of memory |
| D. | none of the mentioned |
| Answer» C. it leads to wastage of memory | |
| Explanation: if the size is more than the required size then the extra space gets wasted. | |
| 339. | The lower order bits of the virtual address forms the |
| A. | page number |
| B. | frame number |
| C. | block number |
| D. | offset |
| Answer» D. offset | |
| Explanation: this gives the offset within the page table. | |
| 340. | The area in the main memory that can hold one page is called as |
| A. | page entry |
| B. | page frame |
| C. | frame |
| D. | block |
| Answer» B. page frame | |
| Explanation: none. | |
| 341. | The starting address of the page table is stored in |
| A. | tlb |
| B. | r0 |
| C. | page table base register |
| D. | none of the mentioned |
| Answer» C. page table base register | |
| Explanation: the register is used to | |
| 342. | The bits used to indicate the status of the page in the memory is called |
| A. | control bits |
| B. | status bits |
| C. | progress bit |
| D. | none of the mentioned |
| Answer» A. control bits | |
| Explanation: these bits are used to store the status information of the program. | |
| 343. | The bit is used to indicate the validity of the page. |
| A. | valid bit |
| B. | invalid bit |
| C. | correct bit |
| D. | none of the mentioned |
| Answer» A. valid bit | |
| Explanation: the os first validates the page and then only moves from the page table. | |
| 344. | The bit used to store whether the page has been modified or not is called as |
| A. | dirty bit |
| B. | modify bit |
| C. | relocation bit |
| D. | none of the mentioned |
| Answer» A. dirty bit | |
| Explanation: this bit is set after the page in the table gets modified. | |
| 345. | The page table should be ideally situated within |
| A. | processor |
| B. | tlb |
| C. | mmu |
| D. | cache |
| Answer» C. mmu | |
| Explanation: the page table information is used for every read and access operation. | |
| 346. | If the page table is large then it is stored in |
| A. | processor |
| B. | main memory |
| C. | disk |
| D. | secondary storage |
| Answer» B. main memory | |
| Explanation: by storing the table on the ram the required operation’s speed is increased. | |
| 347. | When the page table is placed in the main memory, the is used to store the recently accessed pages. |
| A. | mmu |
| B. | tlb |
| C. | r0 |
| D. | table |
| Answer» B. tlb | |
| Explanation: the tlb is used to store the page numbers of the recently accessed pages. | |
| 348. | The TLB is incorporated as part of the |
| A. | processor |
| B. | mmu |
| C. | disk |
| D. | ram |
| Answer» B. mmu | |
| Explanation: none. | |
| 349. | Whenever a request to the page that is not present in the main memory is accessed is triggered. |
| A. | interrupt |
| B. | request |
| C. | page fault |
| D. | none of the mentioned |
| Answer» C. page fault | |
| Explanation: when a page fault is triggered, the os brings the required page into memory. | |
| 351. | register is designated to point to the 68000 processor stack. | |
| A. | a7 register | |
| B. | b2 register | |
| C. | there is no such designation | |
| D. | any general purpose register is selected at random | |
| Answer» A. a7 register | ||
| Explanation: the processor stack is the place used to store the ongoing and upcoming process information | ||
| 352. | The word length in the 68000 computer is |
| A. | 32 bit |
| B. | 64 bit |
| C. | 16 bit |
| D. | 8 bit |
| Answer» C. 16 bit | |
| Explanation: the length of an instruction that can be read or accessed at a time is referred to as word length. | |
| 353. | Is 68000 computer Byte addressable? |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the ability of a system to access the entire data of a process by reading consecutive bytes is called as byte addressability | |
| 354. | The register in 68000 can contain up to bits. |
| A. | 24 |
| B. | 32 |
| C. | 16 |
| D. | 64 |
| Answer» B. 32 | |
| Explanation: none. | |
| 355. | The 68000 has a max of how many data registers? |
| A. | 16 |
| B. | 20 |
| C. | 10 |
| D. | 8 |
| Answer» D. 8 | |
| Explanation: the data registers are solely used for the purpose of storing data items of the process. | |
| 356. | When an operand is stored in a register it is |
| A. | stored in the lower order bits of the register |
| B. | stored in the higher order bits of the register |
| C. | stored in any of the bits at random |
| D. | none of the mentioned |
| Answer» A. stored in the lower order bits of the register | |
| Explanation: the data always gets stored from the lower order to the higher order bits, except in the case of little endian architecture. | |
| 357. | The 68000 uses address assignment. |
| A. | big endian |
| B. | little endian |
| C. | x-little endian |
| D. | x-big endian |
| Answer» A. big endian | |
| Explanation: the way the data gets stored in a memory is called an address assignment. | |
| 358. | The addresses generated by the 68000 is bit. |
| A. | 32 |
| B. | 16 |
| C. | 24 |
| D. | 42 |
| Answer» C. 24 | |
| Explanation: the size of the address is | |
| 359. | Instructions which can handle any type of addressing mode are said to be |
| A. | omniscient |
| B. | orthogonal |
| C. | versatile |
| D. | none of the mentioned |
| Answer» B. orthogonal | |
| Explanation: these instructions do not require the mentioning of any one type of addressing mode. | |
| 360. | The instructions in 68000 can deal with operands of three different sizes. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the operands are of different sizes because of the difference in the values. | |
| 361. | The Branch instruction in 68000 provides how many types of offsets? |
| A. | 3 |
| B. | 1 |
| C. | 0 |
| D. | 2 |
| Answer» D. 2 | |
| Explanation: the branch instruction basically just adds a constant value to the address present in the pc, to change the instruction to be executed. | |
| 362. | The 68000 uses method to access I/O devices buffers. |
| A. | memory mapped |
| B. | i/o mapped |
| C. | buffer mapped |
| D. | none of the mentioned |
| Answer» A. memory mapped | |
| Explanation: in this method, both the i/o device and the memory share a common address space. | |
| 363. | instruction is used to set up a frame pointer for the subroutines in 68000. |
| A. | create |
| B. | link |
| C. | unlk |
| D. | frame |
| Answer» B. link | |
| Explanation: this pointer is used to monitor the stack. | |
| 364. | The LINK instruction is always followed by instruction. |
| A. | mov |
| B. | unlk |
| C. | org |
| D. | movem |
| Answer» D. movem | |
| Explanation: none. | |
| 365. | ARM stands for |
| A. | advanced rate machines |
| B. | advanced risc machines |
| C. | artificial running machines |
| D. | aviary running machines |
| Answer» B. advanced risc machines view more info and meaning of ARM | |
| Explanation: arm is a type of system architecture. | |
| 366. | The main importance of ARM micro- processors is providing operation with |
| A. | low cost and low power consumption |
| B. | higher degree of multi-tasking |
| C. | lower error or glitches |
| D. | efficient memory management |
| Answer» A. low cost and low power consumption | |
| Explanation: the stand alone feature of the arm processors is that they’re economically viable. | |
| 367. | ARM processors where basically designed for |
| A. | main frame systems |
| B. | distributed systems |
| C. | mobile systems |
| D. | super computers |
| Answer» C. mobile systems | |
| Explanation: these arm processors are designed for handheld devices. | |
| 368. | The ARM processors don’t support Byte addressability. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the ability to store data in the form of consecutive bytes. | |
| 369. | The address space in ARM is |
| A. | 224 |
| B. | 264 |
| C. | 216 |
| D. | 232 |
| Answer» D. 232 | |
| Explanation: none. | |
| 370. | The address system supported by ARM systems is/are |
| A. | little endian |
| B. | big endian |
| C. | x-little endian |
| D. | both little & big endian |
| Answer» D. both little & big endian | |
| Explanation: the way in which, the data gets stored in the system or the way of address allocation is called as address system. | |
| 371. | RISC stands for |
| A. | restricted instruction sequencing computer |
| B. | restricted instruction sequential compiler |
| C. | reduced instruction set computer |
| D. | reduced induction set computer |
| Answer» C. reduced instruction set computer | |
| Explanation: this is a system architecture, in which the performance of the system is improved by reducing the size of the instruction set. | |
| 372. | In the ARM, PC is implemented using |
| A. | caches |
| B. | heaps |
| C. | general purpose register |
| D. | stack |
| Answer» C. general purpose register | |
| Explanation: pc is the place where the next instruction about to be executed is stored. | |
| 373. | The additional duplicate register used in ARM machines are called as |
| A. | copied-registers |
| B. | banked registers |
| C. | extra registers |
| D. | extential registers |
| Answer» B. banked registers | |
| Explanation: the duplicate registers are used in situations of context switching. | |
| 374. | The banked registers are used for |
| A. | switching between supervisor and interrupt mode |
| B. | extended storing |
| C. | same as other general purpose registers |
| D. | none of the mentioned |
| Answer» A. switching between supervisor and interrupt mode | |
| Explanation: when switching from one mode to another, instead of storing the register contents somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual registers. | |
| 376. | All instructions in ARM are conditionally executed. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 377. | The addressing mode where the EA of the operand is the contents of Rn is |
| A. | pre-indexed mode |
| B. | pre-indexed with write back mode |
| C. | post-indexed mode |
| D. | none of the mentioned |
| Answer» C. post-indexed mode | |
| Explanation: none. | |
| 378. | The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is |
| A. | ea = [rn] |
| B. | ea = [rn + rm] |
| C. | ea = [rn] + rm |
| D. | ea = [rm] + rn |
| Answer» A. ea = [rn] | |
| Explanation: effective address is the address that the computer acquires from the current instruction being executed. | |
| 379. | symbol is used to signify write back mode. |
| A. | # |
| B. | ^ |
| C. | & |
| D. | ! |
| Answer» D. ! | |
| Explanation: none. | |
| 380. | The instruction, MLA R0,R1,R2,R3 performs |
| A. | r0<-[r1]+[r2]+[r3] |
| B. | r3<-[r0]+[r1]+[r2] |
| C. | r0<-[r1]*[r2]+[r3] |
| D. | r3<-[r0]*[r1]+[r2] |
| Answer» C. r0<-[r1]*[r2]+[r3] | |
| Explanation: the mla instruction is used perform addition and multiplication together. | |
| 381. | instruction is used to get the 1’s complement of the operand. |
| A. | comp |
| B. | bic |
| C. | ~cmp |
| D. | mvn |
| Answer» D. mvn | |
| Explanation: the complement of all the bits of a data is its 1’s compliment. | |
| 382. | The offset used in the conditional branching is bit. |
| A. | 24 |
| B. | 32 |
| C. | 16 |
| D. | 8 |
| Answer» A. 24 | |
| Explanation: the offset is used to get the new branching address of the process. | |
| 383. | The condition to check whether the branch should happen or not is given by |
| A. | the lower order 8 bits of the instruction |
| B. | the higher order 4 bits of the instruction |
| C. | the lower order 4 bits of the instruction |
| D. | the higher order 8 bits of the instruction |
| Answer» B. the higher order 4 bits of the instruction | |
| Explanation: none. | |
| 384. | directive is used to indicate the beginning of the program instruction or data. |
| A. | equ |
| B. | start |
| C. | area |
| D. | space |
| Answer» C. area | |
| Explanation: none. | |
| 385. | directive specifies the start of the execution. |
| A. | start |
| B. | entry |
| C. | main |
| D. | origin |
| Answer» B. entry | |
| Explanation: this directive indicates the beginning of the executable part of the program. | |
| 386. | directives are used to initialize operands. |
| A. | int |
| B. | dataword |
| C. | reserve |
| D. | dcd |
| Answer» D. dcd | |
| Explanation: these directives are used to initialize the operands to a user defined value or a default value. | |
| 387. | directive is used to name the register used for execution of an instruction. |
| A. | assign |
| B. | rn |
| C. | name |
| D. | declare |
| Answer» B. rn | |
| Explanation: this instruction is used to list the registers used for execution. | |
| 388. | The pseudo instruction used to load an address into the register is |
| A. | load |
| B. | adr |
| C. | assign |
| D. | psload |
| Answer» B. adr | |
| Explanation: none. | |
| 389. | The size of the floating registers can be extended upto |
| A. | 128 bit |
| B. | 256 bit |
| C. | 80 bit |
| D. | 64 bit |
| Answer» C. 80 bit | |
| Explanation: none. | |
| 390. | The floating point numbers are stored in general purpose register in IA-32. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the floating registers are not stored in general purpose registers as they have a real part and a decimal part. | |
| 391. | The PC is incorporated with the help of general purpose registers. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: registers are not used to incorporate pc as in other architectures, but a separate space is allocated to it. | |
| 392. | IOPL stands for |
| A. | input/output privilege level |
| B. | input output process link |
| C. | internal output process link |
| D. | internal offset privilege level |
| Answer» A. input/output privilege level | |
| Explanation: this indicates the security | |
| 393. | In IA-32 architecture along with the general flags, the other conditional flags provided are |
| A. | iopl |
| B. | if |
| C. | tf |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: these flags are basically used to check the system for exceptions. | |
| 394. | The register used to serve as PC is called as |
| A. | indirection register |
| B. | instruction pointer |
| C. | r-32 |
| D. | none of the mentioned |
| Answer» B. instruction pointer | |
| Explanation: the pc is used to store the next instruction that is going to be executed. | |
| 395. | The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this switching enables a wide range of operations to be performed. | |
| 396. | The Bit extension of the register is denoted with the help of symbol. |
| A. | $ |
| B. | ` |
| C. | e |
| D. | ~ |
| Answer» C. e | |
| Explanation: this is used to extend the size of the register. | |
| 397. | The instruction, ADD R1, R2, R3 is decoded as |
| A. | r1<-[r1]+[r2]+[r3] |
| B. | r3<-[r1]+[r2] |
| C. | r3<-[r1]+[r2]+[r3] |
| D. | r1<-[r2]+[r3] |
| Answer» D. r1<-[r2]+[r3] | |
| Explanation: none. | |
| 398. | The instruction JG loop does |
| A. | jumps to the memory location loop if the result of the most recent arithmetic op is even |
| B. | jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0 |
| C. | jumps to the memory location loop if the test condition is satisfied with the value of loop |
| D. | none of the mentioned |
| Answer» B. jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0 | |
| Explanation: this instruction is used to cause a branch based on the outcome of the arithmetic operation. | |
| 399. | The LEA mnemonic is used to |
| A. | load the effective address of an instruction |
| B. | load the values of operands onto an accumulator |
| C. | declare the values as global constants |
| D. | store the outcome of the operation at a memory location |
| Answer» A. load the effective address of an instruction | |
| Explanation: the effective address is the address of the memory location required for the execution of the instruction. | |
| 401. | The bit present in the op code, indicating which of the operands is the source is called as |
| A. | src bit |
| B. | indirection bit |
| C. | direction bit |
| D. | frm bit |
| Answer» C. direction bit | |
| Explanation: none. | |
| 402. | The instruction used to cause unconditional jump is |
| A. | ujg |
| B. | jg |
| C. | jmp |
| D. | goto |
| Answer» C. jmp | |
| Explanation: this statement causes a jump from one instruction to another without the condition. | |
| 403. | instruction is used to check the bit of the condition flags. |
| A. | test |
| B. | tb |
| C. | check |
| D. | bt |
| Answer» D. bt | |
| Explanation: this is used to check the condition flags for exceptions. | |
| 404. | .data directive is used |
| A. | to indicate the ending of the data section |
| B. | to indicate the beginning of the data section |
| C. | to declare all the source operands |
| D. | to initialize the operands |
| Answer» B. to indicate the beginning of the data section | |
| Explanation: this is used to indicate the starting of the section of data. | |
| 405. | The instruction used to multiply operands yielding a double integer outcome is |
| A. | mul |
| B. | imul |
| C. | dmul |
| D. | emul |
| Answer» B. imul | |
| Explanation: this instruction is used to carry out multiplication on large integral values. | |
| 406. | SIMD stands for |
| A. | single instruction multiple data |
| B. | simple instruction multiple decoding |
| C. | sequential instruction multiple decoding |
| D. | system information mutable data |
| Answer» A. single instruction multiple data | |
| Explanation: this is the instruction used to perform an operation on multiple types of data. | |
| 407. | In case of multimedia extension instructions, the pixels are encoded into a data item of |
| A. | 16 bit |
| B. | 32 bit |
| C. | 24 bit |
| D. | 8 bit |
| Answer» D. 8 bit | |
| Explanation: none. | |
| 408. | The MMX (Multimedia Extension) operands are stored in |
| A. | general purpose registers |
| B. | banked registers |
| C. | float point registers |
| D. | graphic registers |
| Answer» C. float point registers | |
| Explanation: these operands are used for graphic related operations. | |
| 409. | The division operation in IA-32 is a single operand instruction so it is assumed that |
| A. | the divisor is stored in the eax register |
| B. | the dividend is stored in the eac register |
| C. | the divisor is stored in the accumulator |
| D. | the dividend is stored in the accumulator |
| Answer» A. the divisor is stored in the eax register | |
| Explanation: in the case of a division | |
| 410. | Any condition that causes a processor to stall is called as |
| A. | hazard |
| B. | page fault |
| C. | system error |
| D. | none of the mentioned |
| Answer» A. hazard | |
| Explanation: an hazard causes a delay in the execution process of the processor. | |
| 411. | The stalling of the processor due to the unavailability of the instructions is called as |
| A. | control hazard |
| B. | structural hazard |
| C. | input hazard |
| D. | none of the mentioned |
| Answer» A. control hazard | |
| Explanation: the control hazard also called as instruction hazard is usually caused by a cache miss. | |
| 412. | The contention for the usage of a hardware device is called |
| A. | structural hazard |
| B. | stalk |
| C. | deadlock |
| D. | none of the mentioned |
| Answer» A. structural hazard | |
| Explanation: the processor contends for the usage of the hardware and might enter into a deadlock state. | |
| 413. | The pipeline bubbling is a method used to prevent data hazard and structural hazards. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the periods of time when the unit is idle is called a bubble. | |
| 414. | method is used in centralized systems to perform out of order execution. |
| A. | scorecard |
| B. | score boarding |
| C. | optimizing |
| D. | redundancy |
| Answer» B. score boarding | |
| Explanation: in a scoreboard, the data dependencies of every instruction are logged. instructions are released only when the scoreboard determines that there are no conflicts with previously issued and incomplete instructions. | |
| 415. | The algorithm followed in most of the systems to perform out of order execution is |
| A. | tomasulo algorithm |
| B. | score carding |
| C. | reader-writer algorithm |
| D. | none of the mentioned |
| Answer» A. tomasulo algorithm | |
| Explanation: the tomasulo algorithm is a hardware algorithm developed in 1967 by robert tomasulo from ibm. it allows sequential instructions that would normally be stalled due to certain dependencies to execute non- sequentially (out-of-order execution). | |
| 416. | The problem where process concurrency becomes an issue is called as |
| A. | philosophers problem |
| B. | bakery problem |
| C. | bankers problem |
| D. | reader-writer problem |
| Answer» D. reader-writer problem | |
| Explanation: none. | |
| 417. | The set of loosely connected computers are called as |
| A. | lan |
| B. | wan |
| C. | workstation |
| D. | cluster |
| Answer» D. cluster | |
| Explanation: in a computer cluster all the participating computers work together on a particular task. | |
| 418. | Each computer in a cluster is connected using |
| A. | utp |
| B. | rj-45 |
| C. | stp |
| D. | coaxial cable |
| Answer» B. rj-45 | |
| Explanation: the computers are connected to each other using a lan connector cable. | |
| 419. | The computer cluster architecture emerged as a result of |
| A. | isa |
| B. | workstation |
| C. | super computers |
| D. | distributed systems |
| Answer» D. distributed systems | |
| Explanation: a distributed system is a computer system spread out over a geographic area. | |
| 420. | The software which governs the group of computers is |
| A. | driver rd45 |
| B. | interface ui |
| C. | clustering middleware |
| D. | distributor |
| Answer» C. clustering middleware | |
| Explanation: the software helps to | |
| 421. | The cluster formation in which the work is divided equally among the systems is |
| A. | load-configuration |
| B. | load-division |
| C. | light head |
| D. | both load-configuration and load- division |
| Answer» A. load-configuration | |
| Explanation: this approach the work gets divided among the systems equally. | |
| 422. | In the client server model of the cluster approach is used. |
| A. | load configuration |
| B. | fifo |
| C. | bankers algorithm |
| D. | round robin |
| Answer» D. round robin | |
| Explanation: by using this approach the performance of the cluster can be enhanced. | |
| 423. | The most common modes of communication in clusters are |
| A. | message queues |
| B. | message passing interface |
| C. | pvm |
| D. | both message passing interface and pvm |
| Answer» D. both message passing interface and pvm | |
| Explanation: none. | |
| 424. | The method followed in case of node failure, wherein the node gets disabled is |
| A. | stonith |
| B. | fibre channel |
| C. | fencing |
| D. | none of the mentioned |
| Answer» A. stonith | |
| Explanation: none. | |
| 426. | The main difference between the VLIW and the other approaches to improve performance is | |
| A. | cost effectiveness | |
| B. | increase in performance | |
| C. | lack of complex hardware design | |
| D. | all of the mentioned | |
| Answer» C. lack of complex hardware design | ||
| Explanation: the pipe-lining and super- scalar architectures involved the usage of complex hardware circuits for the implementation. | ||
| 427. | In VLIW the decision for the order of execution of the instructions depends on the program itself. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: in other words, the order of execution of instructions has nothing to do with the physical hardware implementation of the system. | |
| 428. | The parallel execution of operations in VLIW is done according to the schedule determined by |
| A. | task scheduler |
| B. | interpreter |
| C. | compiler |
| D. | encoder |
| Answer» C. compiler | |
| Explanation: the compiler first checks the code for interdependencies and then determines the schedule for its execution. | |
| 429. | The VLIW processors are much simpler as they do not require of |
| A. | computational register |
| B. | complex logic circuits |
| C. | ssd slots |
| D. | scheduling hardware |
| Answer» D. scheduling hardware | |
| Explanation: as the compiler only decides the schedule of execution the schedule is not required here. | |
| 430. | To compute the direction of the branch the VLIW uses |
| A. | seekers |
| B. | heuristics |
| C. | direction counter |
| D. | compass |
| Answer» B. heuristics | |
| Explanation: none. | |
| 431. | EPIC stands for? |
| A. | explicitly parallel instruction computing |
| B. | external peripheral integrating component |
| C. | external parallel instruction computing |
| D. | none of the mentioned |
| Answer» A. explicitly parallel instruction computing | |
| Explanation: none. | |
| 432. | The duration between the read and the mfc signal is |
| A. | access time |
| B. | latency |
| C. | delay |
| D. | cycle time |
| Answer» A. access time | |
| Explanation: the time between the issue of a read signal and the completion of it is called memory access time. | |
| 433. | The minimum time delay between two successive memory read operations is |
| A. | cycle time |
| B. | latency |
| C. | delay |
| D. | none of the mentioned |
| Answer» A. cycle time | |
| Explanation: the time taken by the cpu to end one read operation and to start one more is cycle time. | |
| 434. | is the bottleneck, when it comes computer performance. |
| A. | memory access time |
| B. | memory cycle time |
| C. | delay |
| D. | latency |
| Answer» B. memory cycle time | |
| Explanation: the processor can execute instructions faster than they’re fetched, hence cycle time is the bottleneck for performance. | |
| 435. | The logical addresses generated by the cpu are mapped onto physical memory by |
| A. | relocation register |
| B. | tlb |
| C. | mmu |
| D. | none of the mentioned |
| Answer» C. mmu | |
| Explanation: the mmu stands for memory management unit, which is used to map logical address onto the physical address. | |
| 436. | VLSI stands for |
| A. | very large scale integration |
| B. | very large stand-alone integration |
| C. | volatile layer system interface |
| D. | none of the mentioned |
| Answer» A. very large scale integration | |
| Explanation: none. | |
| 437. | The cells in a row are connected to a common line called |
| A. | work line |
| B. | word line |
| C. | length line |
| D. | principle diagonal |
| Answer» B. word line | |
| Explanation: this means that the cell contents together form one word of instruction or data. | |
| 438. | The cells in each column are connected to |
| A. | word line |
| B. | data line |
| C. | read line |
| D. | sense/ write line |
| Answer» D. sense/ write line | |
| Explanation: the cells in each column are connected to the sense/write circuit using two bit lines and which is in turn connected to the data lines. | |
| 439. | The word line is driven by the |
| A. | chip select |
| B. | address decoder |
| C. | data line |
| D. | control line |
| Answer» B. address decoder | |
| Explanation: none. | |
| 440. | A 16 X 8 Organisation of memory cells, can store upto |
| A. | 256 bits |
| B. | 1024 bits |
| C. | 512 bits |
| D. | 128 bits |
| Answer» D. 128 bits | |
| Explanation: it can store upto 128 bits as each cell can hold one bit of data. | |
| 441. | A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into |
| A. | 128 x 8 |
| B. | 256 x 4 |
| C. | 512 x 2 |
| D. | 1024 x 1 |
| Answer» D. 1024 x 1 | |
| Explanation: all the others require less than 10 address bits. | |
| 442. | Circuits that can hold their state as long as power is applied is |
| A. | dynamic memory |
| B. | static memory |
| C. | register |
| D. | cache |
| Answer» B. static memory | |
| Explanation: none. | |
| 443. | The number of external connections required in 16 X 8 memory organisation is |
| A. | 14 |
| B. | 19 |
| C. | 15 |
| D. | 12 |
| Answer» A. 14 | |
| Explanation: in the 14, 8-data lines,4- address lines and 2 are sense/write and cs signals. | |
| 444. | The advantage of CMOS SRAM over the transistor one’s is |
| A. | low cost |
| B. | high efficiency |
| C. | high durability |
| D. | low power consumption |
| Answer» D. low power consumption | |
| Explanation: this is because the cell consumes power only when it is being accessed. | |
| 445. | In a 4M-bit chip organisation has a total of 19 external connections.then it has address if 8 data lines are there. |
| A. | 10 |
| B. | 8 |
| C. | 9 |
| D. | 12 |
| Answer» C. 9 | |
| Explanation: to have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8 organisation). | |
| 446. | The Reason for the disregarding of the SRAM’s is |
| A. | low efficiency |
| B. | high power consumption |
| C. | high cost |
| D. | all of the mentioned |
| Answer» C. high cost | |
| Explanation: the reason for the high cost of the sram is because of the usage of more number of transistors. | |
| 447. | The disadvantage of DRAM over SRAM is/are |
| A. | lower data storage capacities |
| B. | higher heat dissipation |
| C. | the cells are not static |
| D. | all of the mentioned |
| Answer» C. the cells are not static | |
| Explanation: this means that the cells won’t hold their state indefinitely. | |
| 448. | The reason for the cells to lose their state over time is |
| A. | the lower voltage levels |
| B. | usage of capacitors to store the charge |
| C. | use of shift registers |
| D. | none of the mentioned |
| Answer» B. usage of capacitors to store the charge | |
| Explanation: since capacitors are used the charge dissipates over time. | |
| 449. | The capacitors lose the charge over time due to |
| A. | the leakage resistance of the capacitor |
| B. | the small current in the transistor after being turned on |
| C. | the defect of the capacitor |
| D. | none of the mentioned |
| Answer» A. the leakage resistance of the capacitor | |
| Explanation: the capacitor loses charge due to the backward current of the transistor and due to the small resistance. | |
| 451. | To reduce the number of external connections required, we make use of | |
| A. | de-multiplexer | |
| B. | multiplexer | |
| C. | encoder | |
| D. | decoder | |
| Answer» B. multiplexer | ||
| Explanation: we multiplex the various address lines onto fewer pins. | ||
| 452. | The processor must take into account the delay in accessing the memory location, such memories are called |
| A. | delay integrated |
| B. | asynchronous memories |
| C. | synchronous memories |
| D. | isochronous memories |
| Answer» B. asynchronous memories | |
| Explanation: none. | |
| 453. | To get the row address of the required data is enabled. |
| A. | cas |
| B. | ras |
| C. | cs |
| D. | sense/write |
| Answer» B. ras | |
| Explanation: this makes the contents of the row required refreshed. | |
| 454. | In order to read multiple bytes of a row at the same time, we make use of |
| A. | latch |
| B. | shift register |
| C. | cache |
| D. | memory extension |
| Answer» A. latch | |
| Explanation: the latch makes it easy to ready multiple bytes of data of the same row simultaneously by just giving the consecutive column address. | |
| 455. | The block transfer capability of the DRAM is called |
| A. | burst mode |
| B. | block mode |
| C. | fast page mode |
| D. | fast frame mode |
| Answer» C. fast page mode | |
| Explanation: none. | |
| 456. | The difference between DRAM’s and SDRAM’s is/are |
| A. | the dram’s will not use the master slave relationship in data transfer |
| B. | the sdram’s make use of clock |
| C. | the sdram’s are more power efficient |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| Explanation: the sdram’s make use of clock signals to synchronize their operation. | |
| 457. | The difference in the address and data connection between DRAM’s and SDRAM’s is |
| A. | the usage of more number of pins in sdram’s |
| B. | the requirement of more address lines in sdram’s |
| C. | the usage of a buffer in sdram’s |
| D. | none of the mentioned |
| Answer» C. the usage of a buffer in sdram’s | |
| Explanation: the sdram uses buffered storage of address and data. | |
| 458. | A is used to restore the contents of the cells. |
| A. | sense amplifier |
| B. | refresh counter |
| C. | restorer |
| D. | none of the mentioned |
| Answer» B. refresh counter | |
| Explanation: the counter helps to restore the charge on the capacitor. | |
| 459. | The mode register is used to |
| A. | select the row or column data transfer mode |
| B. | select the mode of operation |
| C. | select mode of storing the data |
| D. | all of the mentioned |
| Answer» B. select the mode of operation | |
| Explanation: the mode register is used to choose between burst mode or bit mode of operation. | |
| 460. | In a SDRAM each row is refreshed every 64ms. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 461. | DDR SDRAM’s perform faster data transfer by |
| A. | integrating the hardware |
| B. | transferring on both edges |
| C. | improving the clock speeds |
| D. | increasing the bandwidth |
| Answer» B. transferring on both edges | |
| Explanation: by transferring data on both the edges the bandwidth is effectively doubled. | |
| 462. | To improve the data retrieval rate |
| A. | access time |
| B. | cycle time |
| C. | memory latency |
| D. | none of the mentioned |
| Answer» C. memory latency | |
| Explanation: the performance of the memory is measured by means of latency. | |
| 463. | In SDRAM’s buffers are used to store data that is read or written. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: in sdram’s all the bytes of data to be read or written are stored in the buffer until the operation is complete. | |
| 464. | The SDRAM performs operation on the |
| A. | rising edge of the clock |
| B. | falling edge of the clock |
| C. | middle state of the clock |
| D. | transition state of the clock |
| Answer» A. rising edge of the clock | |
| Explanation: the sdram’s are edge- | |
| 465. | The chip can be disabled or cut off from an external connection using |
| A. | chip select |
| B. | lock |
| C. | acpt |
| D. | reset |
| Answer» A. chip select | |
| Explanation: the chip gets enabled if the cs is set otherwise the chip gets disabled. | |
| 466. | To organise large memory chips we make use of |
| A. | integrated chips |
| B. | upgraded hardware |
| C. | memory modules |
| D. | none of the mentioned |
| Answer» C. memory modules | |
| Explanation: the cell blocks are arranged and put in a memory module. | |
| 467. | The less space consideration as lead to the development of (for large memories). |
| A. | simm’s |
| B. | dims’s |
| C. | sram’s |
| D. | both simm’s and dims’s |
| Answer» D. both simm’s and dims’s | |
| Explanation: the simm (single inline memory module) or dimm (dual inline memory module) occupy less space while providing greater memory space. | |
| 468. | The SRAM’s are basically used as |
| A. | registers |
| B. | caches |
| C. | tlb |
| D. | buffer |
| Answer» B. caches | |
| Explanation: the sram’s are used as caches as their operation speed is very high. | |
| 469. | The higher order bits of the address are used to |
| A. | specify the row address |
| B. | specify the column address |
| C. | input the cs |
| D. | none of the mentioned |
| Answer» A. specify the row address | |
| Explanation: none. | |
| 470. | The address lines multiplexing is done using |
| A. | mmu |
| B. | memory controller unit |
| C. | page table |
| D. | overlay generator |
| Answer» B. memory controller unit | |
| Explanation: this unit multiplexes the various address lines to lesser pins on the chip. | |
| 471. | The controller multiplexes the addresses after getting the signal. |
| A. | intr |
| B. | ack |
| C. | reset |
| D. | request |
| Answer» D. request | |
| Explanation: the controller gets the request from the device needing the memory read or write operation and then it multiplexes the address. | |
| 472. | The RAS and CAS signals are provided by the |
| A. | mode register |
| B. | cs |
| C. | memory controller |
| D. | none of the mentioned |
| Answer» C. memory controller | |
| Explanation: the multiplexed signal of the controller is split into ras and cas. | |
| 473. | When DRAM’s are used to build a complex large memory, then the controller only provides the refresh counter. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 474. | RAMBUS is better than the other memory chips in terms of |
| A. | efficiency |
| B. | speed of operation |
| C. | wider bandwidth |
| D. | all of the mentioned |
| Answer» B. speed of operation | |
| Explanation: the rambus is much advanced mode of memory storage. | |
| 476. | The increase in operation speed is done by | |
| A. | reducing the reference voltage | |
| B. | increasing the clk frequency | |
| C. | using enhanced hardware | |
| D. | none of the mentioned | |
| Answer» A. reducing the reference voltage | ||
| Explanation: the reference voltage is | ||
| 477. | The data is transferred over the RAMBUS as |
| A. | packets |
| B. | blocks |
| C. | swing voltages |
| D. | bits |
| Answer» C. swing voltages | |
| Explanation: by using voltage swings to transfer data, the transfer rate along with efficiency is improved. | |
| 478. | The type of signaling used in RAMBUS is |
| A. | clk signaling |
| B. | differential signaling |
| C. | integral signaling |
| D. | none of the mentioned |
| Answer» B. differential signaling | |
| Explanation: the differential signaling basically means using voltage swings to transmit data. | |
| 479. | The special communication used in RAMBUS are |
| A. | rambus channel |
| B. | d-link |
| C. | dial-up |
| D. | none of the mentioned |
| Answer» A. rambus channel | |
| Explanation: the special communication link is used to provide the necessary design and required hardware for the transmission. | |
| 480. | The original design of the RAMBUS required for data lines. |
| A. | 4 |
| B. | 6 |
| C. | 8 |
| D. | 9 |
| Answer» D. 9 | |
| Explanation: out of the 9 data lines, 8 were used for data transmission and the one left was used for parity checking. | |
| 481. | The RAMBUS requires specially designed memory chips similar to |
| A. | sram |
| B. | sdram |
| C. | dram |
| D. | ddrram |
| Answer» C. dram | |
| Explanation: the special memory chip should be able to transmit data on both the edges and is called as rdram’s. | |
| 482. | A RAMBUS which has 18 data lines is called as |
| A. | extended rambus |
| B. | direct rambus |
| C. | multiple rambus |
| D. | indirect rambus |
| Answer» B. direct rambus | |
| Explanation: the direct rambus is used to transmit 2 bytes of data at a time. | |
| 483. | The RDRAM chips assembled into larger memory modules called |
| A. | rrim |
| B. | dimm |
| C. | simm |
| D. | all of the mentioned |
| Answer» A. rrim | |
| Explanation: none. | |
| 484. | If the transistor gate is closed, then the ROM stores a value of 1. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: if the gate of the | |
| 485. | PROM stands for |
| A. | programmable read only memory |
| B. | pre-fed read only memory |
| C. | pre-required read only memory |
| D. | programmed read only memory |
| Answer» A. programmable read only memory | |
| Explanation: it allows the user to program the rom. | |
| 486. | The PROM is more effective than ROM chips in regard to |
| A. | cost |
| B. | memory management |
| C. | speed of operation |
| D. | both cost and speed of operation |
| Answer» D. both cost and speed of operation | |
| Explanation: the prom is cheaper than rom as they can be programmed manually. | |
| 487. | The difference between the EPROM and ROM circuitry is |
| A. | the usage of mosfet’s over transistors |
| B. | the usage of jfet’s over transistors |
| C. | the usage of an extra transistor |
| D. | none of the mentioned |
| Answer» C. the usage of an extra transistor | |
| Explanation: the eprom uses an extra transistor where the ground connection is there in the rom chip. | |
| 488. | The ROM chips are mainly used to store |
| A. | system files |
| B. | root directories |
| C. | boot files |
| D. | driver files |
| Answer» C. boot files | |
| Explanation: the rom chips are used to store boot files required for the system startup. | |
| 489. | The contents of the EPROM are erased by |
| A. | overcharging the chip |
| B. | exposing the chip to uv rays |
| C. | exposing the chip to ir rays |
| D. | discharging the chip |
| Answer» B. exposing the chip to uv rays | |
| Explanation: to erase the contents of the eprom the chip is exposed to the uv rays, which dissipate the charge on the transistor. | |
| 490. | The disadvantage of the EPROM chip is |
| A. | the high cost factor |
| B. | the low efficiency |
| C. | the low speed of operation |
| D. | the need to remove the chip physically to reprogram it |
| Answer» D. the need to remove the chip physically to reprogram it | |
| Explanation: none. | |
| 491. | EEPROM stands for Electrically Erasable Programmable Read Only Memory. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the disadvantages of the eprom led to the development of the eeprom. | |
| 492. | The memory devices which are similar to EEPROM but differ in the cost effectiveness is |
| A. | memory sticks |
| B. | blue-ray devices |
| C. | flash memory |
| D. | cmos |
| Answer» C. flash memory | |
| Explanation: the flash memory functions similar to the eeprom but is much cheaper. | |
| 493. | The only difference between the EEPROM and flash memory is that the latter doesn’t allow bulk data to be written. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this is not permitted as the previous contents of the cells will be overwritten. | |
| 494. | The flash memories find application in |
| A. | super computers |
| B. | mainframe systems |
| C. | distributed systems |
| D. | portable devices |
| Answer» D. portable devices | |
| Explanation: the flash memories low power requirement enables them to be used in a wide range of hand held devices. | |
| 495. | The flash memory modules designed to replace the functioning of a hard disk is |
| A. | rimm |
| B. | flash drives |
| C. | fimm |
| D. | dimm |
| Answer» B. flash drives | |
| Explanation: the flash drives have been developed to provide faster operation but with lesser space. | |
| 496. | The reason for the fast operating speeds of the flash drives is |
| A. | the absence of any movable parts |
| B. | the integrated electronic hardware |
| C. | the improved bandwidth connection |
| D. | all of the mentioned |
| Answer» A. the absence of any movable parts | |
| Explanation: since the flash drives have no movable parts their access and seek times are reasonably reduced. | |
| 497. | The standard SRAM chips are costly as |
| A. | they use highly advanced micro- electronic devices |
| B. | they house 6 transistor per chip |
| C. | they require specially designed pcb’s |
| D. | none of the mentioned |
| Answer» B. they house 6 transistor per chip | |
| Explanation: as they require a large number of transistors, their cost per bit increases. | |
| 498. | The drawback of building a large memory with DRAM is |
| A. | the large cost factor |
| B. | the inefficient memory organisation |
| C. | the slow speed of operation |
| D. | all of the mentioned |
| Answer» C. the slow speed of operation | |
| Explanation: the dram’s were used for large memory modules for a long time until a substitute was found. | |
| 499. | To overcome the slow operating speeds of the secondary memory we make use of faster flash drives. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: to improve the speed we use flash drives at the cost of memory space. | |
| 501. | The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called | |
| A. | level 1 cache | |
| B. | level 2 cache | |
| C. | registers | |
| D. | tlb | |
| Answer» A. level 1 cache | ||
| Explanation: these memory devices are generally used to map onto the data stored in the larger memories. | ||
| 502. | The larger memory placed between the primary cache and the memory is called |
| A. | level 1 cache |
| B. | level 2 cache |
| C. | eeprom |
| D. | tlb |
| Answer» B. level 2 cache | |
| Explanation: this is basically used to provide effective memory mapping. | |
| 503. | The next level of memory hierarchy after the L2 cache is |
| A. | secondary storage |
| B. | tlb |
| C. | main memory |
| D. | register |
| Answer» D. register | |
| Explanation: none. | |
| 504. | The last on the hierarchy scale of memory devices is |
| A. | main memory |
| B. | secondary memory |
| C. | tlb |
| D. | flash drives |
| Answer» B. secondary memory | |
| Explanation: the secondary memory is the slowest memory device. | |
| 505. | In the memory hierarchy, as the speed of operation increases the memory size also increases. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: as the speed of operation increases the cost increases and the size decreases. | |
| 506. | If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the flash drives will increase the speed of transfer but still it won’t be faster than primary memory. | |
| 507. | The reason for the implementation of the cache memory is |
| A. | to increase the internal memory of the system |
| B. | the difference in speeds of operation of the processor and memory |
| C. | to reduce the memory access and cycle time |
| D. | all of the mentioned |
| Answer» B. the difference in speeds of operation of the processor and memory | |
| Explanation: this difference in the speeds of operation of the system caused it to be inefficient. | |
| 508. | The effectiveness of the cache memory is based on the property of |
| A. | locality of reference |
| B. | memory localisation |
| C. | memory size |
| D. | none of the mentioned |
| Answer» A. locality of reference | |
| Explanation: this means that the cache | |
| 509. | The temporal aspect of the locality of reference means |
| A. | that the recently executed instruction won’t be executed soon |
| B. | that the recently executed instruction is temporarily not referenced |
| C. | that the recently executed instruction will be executed soon again |
| D. | none of the mentioned |
| Answer» C. that the recently executed instruction will be executed soon again | |
| Explanation: none. | |
| 510. | The spatial aspect of the locality of reference means |
| A. | that the recently executed instruction is executed again next |
| B. | that the recently executed won’t be executed again |
| C. | that the instruction executed will be executed at a later time |
| D. | that the instruction in close proximity of the instruction executed will be executed in future |
| Answer» D. that the instruction in close proximity of the instruction executed will be executed in future | |
| Explanation: the spatial aspect of locality of reference tells that the nearby instruction is more likely to be executed in future. | |
| 511. | The correspondence between the main memory blocks and those in the cache is given by |
| A. | hash function |
| B. | mapping function |
| C. | locale function |
| D. | assign function |
| Answer» B. mapping function | |
| Explanation: the mapping function is used to map the contents of the memory to the cache. | |
| 512. | The algorithm to remove and place new contents into the cache is called |
| A. | replacement algorithm |
| B. | renewal algorithm |
| C. | updation |
| D. | none of the mentioned |
| Answer» A. replacement algorithm | |
| Explanation: as the cache gets full, older contents of the cache are swapped out with newer contents. this decision is taken by the algorithm. | |
| 513. | The write-through procedure is used |
| A. | to write onto the memory directly |
| B. | to write and read from memory simultaneously |
| C. | to write directly on the memory and the cache simultaneously |
| D. | none of the mentioned |
| Answer» C. to write directly on the memory and the cache simultaneously | |
| Explanation: when write operation is issued then the corresponding operation is performed. | |
| 514. | The bit used to signify that the cache location is updated is |
| A. | dirty bit |
| B. | update bit |
| C. | reference bit |
| D. | flag bit |
| Answer» A. dirty bit | |
| Explanation: when the cache location is updated in order to signal to the processor this bit is used. | |
| 515. | The copy-back protocol is used |
| A. | to copy the contents of the memory onto the cache |
| B. | to update the contents of the memory from the cache |
| C. | to remove the contents of the cache and push it on to the memory |
| D. | none of the mentioned |
| Answer» B. to update the contents of the memory from the cache | |
| Explanation: this is another way of performing the write operation, wherein the cache is updated first and then the memory. | |
| 516. | The approach where the memory contents are transferred directly to the processor from the memory is called |
| A. | read-later |
| B. | read-through |
| C. | early-start |
| D. | none of the mentioned |
| Answer» C. early-start | |
| Explanation: none. | |
| 517. | In protocol the information is directly written into the main memory. |
| A. | write through |
| B. | write back |
| C. | write first |
| D. | none of the mentioned |
| Answer» A. write through | |
| Explanation: in case of the miss, then the data gets written directly in main memory. | |
| 518. | The only draw back of using the early start protocol is |
| A. | time delay |
| B. | complexity of circuit |
| C. | latency |
| D. | high miss rate |
| Answer» B. complexity of circuit | |
| Explanation: in this protocol, the required block is read and directly sent to the processor. | |
| 519. | During a write operation if the required block is not present in the cache then occurs. |
| A. | write latency |
| B. | write hit |
| C. | write delay |
| D. | write miss |
| Answer» D. write miss | |
| Explanation: this indicates that the | |
| 520. | While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for |
| A. | tag |
| B. | block |
| C. | word |
| D. | id |
| Answer» A. tag | |
| Explanation: the tag is used to identify the block mapped onto one particular cache block. | |
| 521. | In direct mapping the presence of the block in memory is checked with the help of block field. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the tag field is used to check the presence of a mem block. | |
| 522. | In associative mapping, in a 16 bit system the tag field has bits. |
| A. | 12 |
| B. | 8 |
| C. | 9 |
| D. | 10 |
| Answer» A. 12 | |
| Explanation: the tag field is used as an id for the different memory blocks mapped to the cache. | |
| 523. | The associative mapping is costlier than direct mapping. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: in associative mapping, all the tags have to be searched to find the block. | |
| 524. | The technique of searching for a block by going through all the tags is |
| A. | linear search |
| B. | binary search |
| C. | associative search |
| D. | none of the mentioned |
| Answer» C. associative search | |
| Explanation: none. | |
| 526. | In set-associative technique, the blocks are grouped into sets. |
| A. | 4 |
| B. | 8 |
| C. | 12 |
| D. | 6 |
| Answer» D. 6 | |
| Explanation: the set-associative technique groups the blocks into different sets. | |
| 527. | A control bit called has to be provided to each block in set- associative. |
| A. | idol bit |
| B. | valid bit |
| C. | reference bit |
| D. | all of the mentioned |
| Answer» B. valid bit | |
| Explanation: the valid bit is used to indicate that the block holds valid information. | |
| 528. | The bit used to indicate whether the block was recently used or not is |
| A. | idol bit |
| B. | control bit |
| C. | reference bit |
| D. | dirty bit |
| Answer» D. dirty bit | |
| Explanation: the dirty bit is used to show that the block was recently modified and for a replacement algorithm. | |
| 529. | Data which is not up-to date is called as |
| A. | spoilt data |
| B. | stale data |
| C. | dirty data |
| D. | none of the mentioned |
| Answer» B. stale data | |
| Explanation: none. | |
| 530. | The main memory is structured into modules each with its own address register called |
| A. | abr |
| B. | tlb |
| C. | pc |
| D. | ir |
| Answer» A. abr | |
| Explanation: abr stands for address buffer register. | |
| 531. | When consecutive memory locations are accessed only one module is accessed at a time. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: in a modular approach to memory structuring only one module can be accessed at a time. | |
| 532. | In memory interleaving, the lower order bits of the address is used to |
| A. | get the data |
| B. | get the address of the module |
| C. | get the address of the data within the module |
| D. | none of the mentioned |
| Answer» B. get the address of the module | |
| Explanation: to implement parallelism in data access we use interleaving. | |
| 533. | The number successful accesses to memory stated as a fraction is called as |
| A. | hit rate |
| B. | miss rate |
| C. | success rate |
| D. | access rate |
| Answer» A. hit rate | |
| Explanation: the hit rate is an important factor in performance measurement. | |
| 534. | The number failed attempts to access memory, stated in the form of a fraction is called as |
| A. | hit rate |
| B. | miss rate |
| C. | failure rate |
| D. | delay rate |
| Answer» B. miss rate | |
| Explanation: the miss rate is a key factor in deciding the type of replacement algorithm. | |
| 535. | In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when occurs. |
| A. | delay |
| B. | miss |
| C. | hit |
| D. | delayed hit |
| Answer» B. miss | |
| Explanation: miss usually occurs when the memory block required is not present in the cache. | |
| 536. | In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of |
| A. | hit |
| B. | miss |
| C. | delay |
| D. | none of the mentioned |
| Answer» A. hit | |
| Explanation: if the referenced block is present in the memory it is called as hit. | |
| 537. | If hit rates are well below 0.9, then they’re called as speedy computers. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: it has to be above 0.9 for speedy computers. | |
| 538. | The extra time needed to bring the data into memory in case of a miss is called as |
| A. | delay |
| B. | propagation time |
| C. | miss penalty |
| D. | none of the mentioned |
| Answer» C. miss penalty | |
| Explanation: none. | |
| 539. | The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the extra time needed to bring the data into memory in case of a miss is called as miss penalty. | |
| 540. | The CPU is also called as |
| A. | processor hub |
| B. | isp |
| C. | controller |
| D. | all of the mentioned |
| Answer» B. isp | |
| Explanation: isp stands for instruction set processor. | |
| 541. | A common strategy for performance is making various functional units operate parallelly. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: by parallelly accessing data we can have a pipelined processor. | |
| 542. | The PC gets incremented |
| A. | after the instruction decoding |
| B. | after the ir instruction gets executed |
| C. | after the fetch cycle |
| D. | none of the mentioned |
| Answer» C. after the fetch cycle | |
| Explanation: the pc always points to the next instruction to be executed. | |
| 543. | Which register in the processor is single directional? |
| A. | mar |
| B. | mdr |
| C. | pc |
| D. | temp |
| Answer» A. mar | |
| Explanation: the mar is single directional as it just takes the address from the processor bus and passes it to the external bus. | |
| 544. | The transparent register/s is/are |
| A. | y |
| B. | z |
| C. | temp |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: these registers are usually used to store temporary values. | |
| 545. | Which register is connected to the MUX? |
| A. | y |
| B. | z |
| C. | r0 |
| D. | temp |
| Answer» A. y | |
| Explanation: the mux can either read the operand from the y register or increment the pc. | |
| 546. | The registers, ALU and the interconnecting path together are called as |
| A. | control path |
| B. | flow path |
| C. | data path |
| D. | none of the mentioned |
| Answer» C. data path | |
| Explanation: none. | |
| 547. | The input and output of the registers are governed by |
| A. | transistors |
| B. | diodes |
| C. | gates |
| D. | switches |
| Answer» D. switches | |
| Explanation: none. | |
| 548. | When two or more clock cycles are used to complete data transfer it is called as |
| A. | single phase clocking |
| B. | multi-phase clocking |
| C. | edge triggered clocking |
| D. | none of the mentioned |
| Answer» B. multi-phase clocking | |
| Explanation: this is basically used in systems without edge-triggered flip flops. | |
| 549. | signal is used to show complete of memory operation. |
| A. | mfc |
| B. | wmfc |
| C. | cfc |
| D. | none of the mentioned |
| Answer» A. mfc | |
| Explanation: mfc stands for memory function complete. | |
| 551. | The small extremely fast, RAM’s all called as |
| A. | cache |
| B. | heaps |
| C. | accumulators |
| D. | stacks |
| Answer» B. heaps | |
| Explanation: cache’s are extremely essential in single bus organisation to achieve fast operation. | |
| 552. | To extend the connectivity of the processor bus we use |
| A. | pci bus |
| B. | scsi bus |
| C. | controllers |
| D. | multiple bus |
| Answer» A. pci bus | |
| Explanation: the pci bus basically is used to connect to memory devices. | |
| 553. | The bus used to connect the monitor to the CPU is |
| A. | pci bus |
| B. | scsi bus |
| C. | memory bus |
| D. | rambus |
| Answer» B. scsi bus | |
| Explanation: the scsi (small component system interconnect) is used to connect to display devices. | |
| 554. | ANSI stands for |
| A. | american national standards institute |
| B. | american national standard interface |
| C. | american network standard interfacing |
| D. | american network security interrupt |
| Answer» A. american national standards institute | |
| Explanation: it is one of the standards of developing a bus. | |
| 555. | The general purpose registers are combined into a block called as |
| A. | register bank |
| B. | register case |
| C. | register file |
| D. | none of the mentioned |
| Answer» C. register file | |
| Explanation: to make the access of the | |
| 556. | In technology, the implementation of the register file is by using an array of memory locations. |
| A. | vlsi |
| B. | ansi |
| C. | isa |
| D. | asci |
| Answer» A. vlsi | |
| Explanation: by doing so the access of the registers can be made faster. | |
| 557. | In a three BUS architecture, how many input and output ports are there? |
| A. | 2 output and 2 input |
| B. | 1 output and 2 input |
| C. | 2 output and 1 input |
| D. | 1 output and 1 input |
| Answer» C. 2 output and 1 input | |
| Explanation: that is enabling reading from two locations and writing into one. | |
| 558. | CISC stands for |
| A. | complete instruction sequential compilation |
| B. | computer integrated sequential compiler |
| C. | complex instruction set computer |
| D. | complex instruction sequential compilation |
| Answer» C. complex instruction set computer | |
| Explanation: the cisc machines are well adept at handling multiple bus organisation. | |
| 559. | There exists a separate block consisting of various units to decode an instruction. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this block is used to decode the instruction and place it in the ir. | |
| 560. | There exists a separate block to increment the PC in multiple BUS organisation. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 561. | are the different type/s of generating control signals. |
| A. | micro-programmed |
| B. | hardwired |
| C. | micro-instruction |
| D. | both micro-programmed and hardwired |
| Answer» D. both micro-programmed and hardwired | |
| Explanation: the above is used to generate control signals in different types of system architectures. | |
| 562. | The type of control signal is generated based on |
| A. | contents of the step counter |
| B. | contents of ir |
| C. | contents of condition flags |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: based on the information above the type of control signal is decided. | |
| 563. | What does the hardwired control generator consist of? |
| A. | decoder/encoder |
| B. | condition codes |
| C. | control step counter |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the cu uses the above blocks and ir to produce the necessary signal. | |
| 564. | What does the end instruction do? |
| A. | it ends the generation of a signal |
| B. | it ends the complete generation process |
| C. | it starts a new instruction fetch cycle and resets the counter |
| D. | it is used to shift the control to the processor |
| Answer» C. it starts a new instruction fetch cycle and resets the counter | |
| Explanation: it is basically used to start the generation of a new signal. | |
| 565. | BR… |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the signal is generated using the logic of the formula above. | |
| 566. | The name hardwired came because the sequence of operations carried out is determined by the wiring. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: in other words hardwired is another name for hardware control signal generator. | |
| 567. | The benefit of using this approach is |
| A. | it is cost effective |
| B. | it is highly efficient |
| C. | it is very reliable |
| D. | it increases the speed of operation |
| Answer» D. it increases the speed of operation | |
| Explanation: none. | |
| 568. | The disadvantage/s of the hardwired approach is |
| A. | it is less flexible |
| B. | it cannot be used for complex instructions |
| C. | it is costly |
| D. | less flexible & cannot be used for complex instructions |
| Answer» D. less flexible & cannot be used for complex instructions | |
| Explanation: the more complex the instruction set less applicable to a hardwired approach. | |
| 569. | In micro-programmed approach, the signals are generated by |
| A. | machine instructions |
| B. | system programs |
| C. | utility tools |
| D. | none of the mentioned |
| Answer» A. machine instructions | |
| Explanation: the machine instructions generate the signals. | |
| 570. | A word whose individual bits represent a control signal is |
| A. | command word |
| B. | control word |
| C. | co-ordination word |
| D. | generation word |
| Answer» B. control word | |
| Explanation: the control word is used to get the different types of control signals required. | |
| 571. | A sequence of control words corresponding to a control sequence is called |
| A. | micro routine |
| B. | micro function |
| C. | micro procedure |
| D. | none of the mentioned |
| Answer» A. micro routine | |
| Explanation: the micro routines are used to perform a particular task. | |
| 572. | Individual control words of the micro routine are called as |
| A. | micro task |
| B. | micro operation |
| C. | micro instruction |
| D. | micro command |
| Answer» C. micro instruction | |
| Explanation: the each instruction which put together performs the task. | |
| 573. | The special memory used to store the micro routines of a computer is |
| A. | control table |
| B. | control store |
| C. | control mart |
| D. | control shop |
| Answer» B. control store | |
| Explanation: the control store is used as a reference to get the required control routine. | |
| 574. | Every time a new instruction is loaded into IR the output of is loaded into UPC. |
| A. | starting address generator |
| B. | loader |
| C. | linker |
| D. | clock |
| Answer» A. starting address generator | |
| Explanation: the starting address generator is used to load the address of the next micro instruction. | |
| 576. | The signals are grouped such that mutually exclusive signals are put together. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this is done to improve the efficiency of the controller. | |
| 577. | Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is |
| A. | horizontal organisation |
| B. | vertical organisation |
| C. | diagonal organisation |
| D. | none of the mentioned |
| Answer» B. vertical organisation | |
| Explanation: none. | |
| 578. | The directly mapped cache no replacement algorithm is required. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the position of each block is pre-determined in the direct mapped cache, hence no need for replacement. | |
| 579. | In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one when occurs. |
| A. | delay |
| B. | miss |
| C. | hit |
| D. | delayed hit |
| Answer» B. miss | |
| Explanation: miss usually occurs when the memory block required is not present in the cache. | |
| 580. | In set associative and associative mapping there exists less flexibility. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the above two methods of mapping the decision of which block to be removed rests with the cache controller. | |
| 581. | The algorithm which replaces the block which has not been referenced for a while is called |
| A. | lru |
| B. | orf |
| C. | direct |
| D. | both lru and orf |
| Answer» A. lru | |
| Explanation: lru stands for least recently used first. | |
| 582. | The algorithm which removes the recently used page first is |
| A. | lru |
| B. | mru |
| C. | ofm |
| D. | none of the mentioned |
| Answer» B. mru | |
| Explanation: in mru it is assumed that the page accessed now is less likely to be accessed again. | |
| 583. | The LRU can be improved by providing a little randomness in the access. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 584. | The counter that keeps track of how many times a block is most likely used is |
| A. | count |
| B. | reference counter |
| C. | use counter |
| D. | probable counter |
| Answer» B. reference counter | |
| Explanation: none. | |
| 585. | The key factor/s in commercial success of a computer is/are |
| A. | performance |
| B. | cost |
| C. | speed |
| D. | both performance and cost |
| Answer» D. both performance and cost | |
| Explanation: the performance and cost of the computer system is a key decider in the commercial success of the system. | |
| 586. | A common measure of performance is |
| A. | price/performance ratio |
| B. | performance/price ratio |
| C. | operation/price ratio |
| D. | none of the mentioned |
| Answer» A. price/performance ratio | |
| Explanation: if this measure is less than one then the system is optimal. | |
| 587. | The performance depends on |
| A. | the speed of execution only |
| B. | the speed of fetch and execution |
| C. | the speed of fetch only |
| D. | the hardware of the system only |
| Answer» B. the speed of fetch and execution | |
| Explanation: the performance of a system is decided by how quick an instruction is brought into the system and executed. | |
| 588. | The main purpose of having memory hierarchy is to |
| A. | reduce access time |
| B. | provide large capacity |
| C. | reduce propagation time |
| D. | reduce access time & provide large capacity |
| Answer» D. reduce access time & provide large capacity | |
| Explanation: by using the memory hierarchy, we can increase the performance of the system. | |
| 589. | The memory transfers between two variable speed devices are always done at the speed of the faster device. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 590. | An effective to introduce parallelism in memory access is by |
| A. | memory interleaving |
| B. | tlb |
| C. | pages |
| D. | frames |
| Answer» A. memory interleaving | |
| Explanation: interleaving divides the memory into modules. | |
| 591. | The performance of the system is greatly influenced by increasing the level 1 cache. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this is so because the l1 cache is onboard the processor. | |
| 592. | Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster. |
| A. | a |
| B. | b |
| C. | both take the same time |
| D. | insufficient information |
| Answer» A. a | |
| Explanation: none. | |
| 593. | If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is a term of the Basic performance equation). |
| A. | 3 |
| B. | ~2 |
| C. | ~1 |
| D. | 6 |
| Answer» C. ~1 | |
| Explanation: pipelining is a process of fetching an instruction during the execution of other instruction. | |
| 594. | The physical memory is not as large as the address space spanned by the processor. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this is one of the main reasons for the usage of virtual memories. | |
| 595. | The program is divided into operable parts called as |
| A. | frames |
| B. | segments |
| C. | pages |
| D. | sheets |
| Answer» B. segments | |
| Explanation: the program is divided into parts called as segments for ease of execution. | |
| 596. | The techniques which move the program blocks to or from the physical memory is called as |
| A. | paging |
| B. | virtual memory organisation |
| C. | overlays |
| D. | framing |
| Answer» B. virtual memory organisation | |
| Explanation: by using this technique the program execution is accomplished with a usage of less space. | |
| 597. | The binary address issued to data or instructions are called as |
| A. | physical address |
| B. | location |
| C. | relocatable address |
| D. | logical address |
| Answer» D. logical address | |
| Explanation: the logical address is the random address generated by the processor. | |
| 598. | is used to implement virtual memory organisation. |
| A. | page table |
| B. | frame table |
| C. | mmu |
| D. | none of the mentioned |
| Answer» C. mmu | |
| Explanation: the mmu stands for memory management unit. | |
| 599. | translates the logical address into a physical address. |
| A. | mmu |
| B. | translator |
| C. | compiler |
| D. | linker |
| Answer» A. mmu | |
| Explanation: the mmu translates the logical address into a physical address by adding an offset. | |
| 601. | The virtual memory basically stores the next segment of data to be executed on the | |
| A. | secondary storage | |
| B. | disks | |
| C. | ram | |
| D. | rom | |
| Answer» A. secondary storage | ||
| Explanation: none. | ||
| 602. | The associatively mapped virtual memory makes use of |
| A. | tlb |
| B. | page table |
| C. | frame table |
| D. | none of the mentioned |
| Answer» A. tlb | |
| Explanation: tlb stands for translation look-aside buffer. | |
| 603. | The main reason for the discontinuation of semi conductor based storage devices for providing large storage space is |
| A. | lack of sufficient resources |
| B. | high cost per bit value |
| C. | lack of speed of operation |
| D. | none of the mentioned |
| Answer» B. high cost per bit value | |
| Explanation: in the case of semi conductor based memory technology, we get speed but the increase in the integration of various devices the cost is high. | |
| 604. | The digital information is stored on the hard disk by |
| A. | applying a suitable electric pulse |
| B. | applying a suitable magnetic field |
| C. | applying a suitable nuclear field |
| D. | by using optic waves |
| Answer» A. applying a suitable electric pulse | |
| Explanation: the digital data is sorted on the magnetized discs by magnetizing the areas. | |
| 605. | For the synchronization of the read head, we make use of a |
| A. | framing bit |
| B. | synchronization bit |
| C. | clock |
| D. | dirty bit |
| Answer» C. clock | |
| Explanation: the clock makes it easy to distinguish between different values red by a head. | |
| 606. | One of the most widely used schemes of encoding used is |
| A. | nrz-polar |
| B. | rz-polar |
| C. | manchester |
| D. | block encoding |
| Answer» C. manchester | |
| Explanation: the manchester encoding used is also called as phase encoding and it is used to encode both clock and data. | |
| 607. | The drawback of Manchester encoding is |
| A. | the cost of the encoding scheme |
| B. | the speed of encoding the data |
| C. | the latency offered |
| D. | the low bit storage density provided |
| Answer» D. the low bit storage density provided | |
| Explanation: the space required to represent each bit must be large enough to accommodate two changes in magnetization. | |
| 608. | The read/write heads must be near to disk surfaces for better storage. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: by maintaining the heads near to the surface greater bit densities can be achieved. | |
| 609. | pushes the heads away from the surface as they rotate at their standard rates. |
| A. | magnetic tension |
| B. | electric force |
| C. | air pressure |
| D. | none of the mentioned |
| Answer» C. air pressure | |
| Explanation: due to the speed of rotation of the discs air pressure develops in the hard disk. | |
| 610. | The air pressure can be countered by putting in the head-disc surface arrangement. |
| A. | air filter |
| B. | spring mechanism |
| C. | coolant |
| D. | none of the mentioned |
| Answer» B. spring mechanism | |
| Explanation: the spring mechanism | |
| 611. | The method of placing the heads and the discs in an air tight environment is also called as |
| A. | raid arrays |
| B. | atp tech |
| C. | winchester technology |
| D. | fleming reduction |
| Answer» C. winchester technology | |
| Explanation: the disks and the heads operate faster due to the absence of the dust particles. | |
| 612. | A hard disk with 20 surfaces will have heads. |
| A. | 10 |
| B. | 5 |
| C. | 1 |
| D. | 20 |
| Answer» D. 20 | |
| Explanation: each surface will have its own head to perform read/write operation. | |
| 613. | The set of corresponding tracks on all surfaces of a stack of disks form a |
| A. | cluster |
| B. | cylinder |
| C. | group |
| D. | set |
| Answer» B. cylinder | |
| Explanation: the data is stored in these sections called as cylinders. | |
| 614. | The data can be accessed from the disk using |
| A. | surface number |
| B. | sector number |
| C. | track number |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: none. | |
| 615. | The read and write operations usually start at of the sector. |
| A. | center |
| B. | middle |
| C. | from the last used point |
| D. | boundaries |
| Answer» D. boundaries | |
| Explanation: the heads read and write data from the ends to the center. | |
| 616. | To distinguish between two sectors we make use of |
| A. | inter sector gap |
| B. | splitting bit |
| C. | numbering bit |
| D. | none of the mentioned |
| Answer» A. inter sector gap | |
| Explanation: this means that we leave a little gap between each sector to differentiate between them. | |
| 617. | The process divides the disk into sectors and tracks. |
| A. | creation |
| B. | initiation |
| C. | formatting |
| D. | modification |
| Answer» C. formatting | |
| Explanation: the formatting process deletes the data present and does the creation of sectors and tracks. | |
| 618. | The access time is composed of |
| A. | seek time |
| B. | rotational delay |
| C. | latency |
| D. | both seek time and rotational delay |
| Answer» D. both seek time and rotational delay | |
| Explanation: the seek time refers to the time required to move the head to the required disk. | |
| 619. | The disk drive is connected to the system by using the |
| A. | pci bus |
| B. | scsi bus |
| C. | hdmi |
| D. | isa |
| Answer» B. scsi bus | |
| Explanation: none. | |
| 620. | is used to deal with the difference in the transfer rates between the drive and the bus. |
| A. | data repeaters |
| B. | enhancers |
| C. | data buffers |
| D. | none of the mentioned |
| Answer» C. data buffers | |
| Explanation: the buffers are added to store the data from the fast device and to send it to the slower device at its rate. | |
| 621. | is used to detect and correct the errors that may occur during data transfers. |
| A. | ecc |
| B. | crc |
| C. | checksum |
| D. | none of the mentioned |
| Answer» A. ecc | |
| Explanation: ecc stands for error correcting code. | |
| 622. | ______ has been developed specifically for pipelined systems. |
| A. | Utility software |
| B. | Speed up utilities |
| C. | Optimizing compilers |
| D. | None of the mentioned |
| Answer» C. Optimizing compilers | |
| 623. | The fetch and execution cycles are interleaved with the help of ________ |
| A. | Modification in processor architecture |
| B. | Clock |
| C. | Special unit |
| D. | Control unit |
| Answer» B. Clock | |
| 624. | Each stage in pipelining should be completed within ____ cycle. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» A. 1 | |
| 626. | The situation wherein the data of operands are not available is called ______ |
| A. | Data hazard |
| B. | Stock |
| C. | Deadlock |
| D. | Structural hazard |
| Answer» A. Data hazard | |
| 627. | The time lost due to the branch instruction is often referred to as _____ |
| A. | Latency |
| B. | Delay |
| C. | Branch penalty |
| D. | None of the mentioned |
| Answer» C. Branch penalty | |
| 628. | The algorithm followed in most of the systems to perform out of order execution is ______ |
| A. | Tomasulo algorithm |
| B. | Score carding |
| C. | Reader-writer algorithm |
| D. | None of the mentioned |
| Answer» A. Tomasulo algorithm | |
| 629. | The logic operations are implemented using _______ circuits. |
| A. | Bridge |
| B. | Logical |
| C. | Combinatorial |
| D. | Gate |
| Answer» C. Combinatorial | |
| 630. | The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________ |
| A. | Half adders |
| B. | Full adders |
| C. | Ripple adders |
| D. | Fast adders |
| Answer» B. Full adders | |
| 631. | Which option is true regarding the carry in the ripple adders? |
| A. | Are generated at the beginning only |
| B. | Must travel through the configuration |
| C. | Is generated at the end of each operation |
| D. | None of the mentioned |
| Answer» B. Must travel through the configuration | |
| 632. | In full adders the sum circuit is implemented using ________ |
| A. | And & or gates |
| B. | NAND gate |
| C. | XOR |
| D. | XNOR |
| Answer» C. XOR | |
| 633. | The usual implementation of the carry circuit involves _________ |
| A. | And & or gates |
| B. | XOR |
| C. | NAND |
| D. | XNOR |
| Answer» B. XOR | |
| 634. | The advantage of I/O mapped devices to memory mapped is ___________ |
| A. | The former offers faster transfer of data |
| B. | The devices connected using I/O mapping have a bigger buffer space |
| C. | The devices have to deal with fewer address lines |
| D. | No advantage as such |
| Answer» C. The devices have to deal with fewer address lines | |
| 635. | The system is notified of a read or write operation by ___________ |
| A. | Appending an extra bit of the address |
| B. | Enabling the read or write bits of the devices |
| C. | Raising an appropriate interrupt signal |
| D. | Sending a special signal along the BUS |
| Answer» D. Sending a special signal along the BUS | |
| 636. | To overcome the lag in the operating speeds of the I/O device and the processor we use ___________ |
| A. | Buffer spaces |
| B. | Status flags |
| C. | Interrupt signals |
| D. | Exceptions |
| Answer» B. Status flags | |
| 637. | The method which offers higher speeds of I/O transfers is ___________ |
| A. | Interrupts |
| B. | Memory mapping |
| C. | Program-controlled I/O |
| D. | DMA |
| Answer» D. DMA | |
| 638. | The instruction, Add #45, R1 does _______ |
| A. | Adds the value of 45 to the address of R1 and stores 45 in that address |
| B. | Adds 45 to the value of R1 and stores it in R1 |
| C. | Finds the memory location 45 and adds that content to that of R1 |
| D. | None of the mentioned |
| Answer» B. Adds 45 to the value of R1 and stores it in R1 | |
| 639. | In the case of, Zero-address instruction method the operands are stored in _____ |
| A. | Registers |
| B. | Accumulators |
| C. | Push down stack |
| D. | Cache |
| Answer» C. Push down stack | |
| 640. | The addressing mode which makes use of in-direction pointers is ______ |
| A. | Indirect addressing mode |
| B. | Index addressing mode |
| C. | Relative addressing mode |
| D. | Offset addressing mode |
| Answer» A. Indirect addressing mode | |
| 641. | The addressing mode/s, which uses the PC instead of a general purpose register is ______ |
| A. | Indexed with offset |
| B. | Relative |
| C. | direct |
| D. | both Indexed with offset and direct |
| Answer» B. Relative | |
| 642. | _____ addressing mode is most suitable to change the normal sequence of execution of instructions. |
| A. | Relative |
| B. | Indirect |
| C. | Index with Offset |
| D. | Immediate |
| Answer» A. Relative | |
| 643. | The reason for the implementation of the cache memory is ________ |
| A. | To increase the internal memory of the system |
| B. | The difference in speeds of operation of the processor and memory |
| C. | To reduce the memory access and cycle time |
| D. | All of the mentioned |
| Answer» B. The difference in speeds of operation of the processor and memory | |
| 644. | The effectiveness of the cache memory is based on the property of ________ |
| A. | Locality of reference |
| B. | Memory localisation |
| C. | Memory size |
| D. | None of the mentioned |
| Answer» A. Locality of reference | |
| 645. | The spatial aspect of the locality of reference means ________ |
| A. | That the recently executed instruction is executed again next |
| B. | That the recently executed won’t be executed again |
| C. | That the instruction executed will be executed at a later time |
| D. | That the instruction in close proximity of the instruction executed will be executed in future |
| Answer» D. That the instruction in close proximity of the instruction executed will be executed in future | |
| 646. | The correspondence between the main memory blocks and those in the cache is given by _________ |
| A. | Hash function |
| B. | Mapping function |
| C. | Locale function |
| D. | Assign function |
| Answer» B. Mapping function | |
| 647. | The copy-back protocol is used ________ |
| A. | To copy the contents of the memory onto the cache |
| B. | To update the contents of the memory from the cache |
| C. | To remove the contents of the cache and push it on to the memory |
| D. | None of the mentioned |
| Answer» B. To update the contents of the memory from the cache | |
| 648. | The address space is 22 bits the memory is 32 bit word addressable what is the memory size |
| A. | 16MB |
| B. | 512KB |
| C. | 4MB |
| D. | 1GB |
| Answer» A. 16MB | |
| 649. | In which cycle the memory is read and the contents of memory at the address containedin the PC register are loaded into in to IR. |
| A. | Execution Cycle |
| B. | Memory Cycle |
| C. | Fetch Cycle |
| D. | Decode Cycle |
| Answer» C. Fetch Cycle | |
| 651. | A system program that combines the separately compiled modules of a program into a form suitable for execution |
| A. | assembler |
| B. | linking loader |
| C. | cross compiler |
| D. | load and go |
| Answer» B. linking loader | |
| 652. | Which parameter of computer determines its power to do various operations on data items |
| A. | Instruction set |
| B. | Memory size |
| C. | Assembly language |
| D. | Application language |
| Answer» A. Instruction set | |
| 653. | The multiplier is stored in |
| A. | PC Register |
| B. | Shift Register |
| C. | Cache |
| D. | None of the above |
| Answer» B. Shift Register | |
| 654. | Which methods of representation of numbers occupies large amount of memory than others? |
| A. | sign-magnitude |
| B. | 1’s compliment |
| C. | 2’s compliment |
| D. | Both a and b |
| Answer» A. sign-magnitude | |
| 655. | The register used to store the flags is called as |
| A. | Flag register |
| B. | Status register |
| C. | Test register |
| D. | log register |
| Answer» B. Status register | |
| 656. | __________is used to implement virtual memory organization. |
| A. | Page table |
| B. | Frame table |
| C. | MMU |
| D. | None of the mentioned |
| Answer» C. MMU | |
| 657. | _________ method is used to establish priority by serially connecting all devices that request an interrupt. |
| A. | Vectored-interrupting |
| B. | Daisy chain |
| C. | Priority |
| D. | Polling |
| Answer» B. Daisy chain | |
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