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On: July 6, 2023 Posted in Digital Comments: 0 Views: 81

Digital Electronics and Logic Design Solved MCQs

1.	The 2s compliment form (Use 6 bit word) of the number 1010 is
A.	111100
B.	110110
C.	110111
D.	1011
Answer» B. 110110

2.	AB+(A+B)’ is equivalent to
A.	a ex-nor b
B.	a ex or b
C.	(a+b)a
D.	(a+b)b
Answer» A. a ex-nor b

3.	The hexadecimal number equivalent to (1762.46)8 is
A.	3f2.89
B.	3f2.98
C.	2f3.89
D.	2f3.98
Answer» B. 3f2.98

4.	A three input NOR gate gives logic high output only when
A.	one input is high
B.	one input is low
C.	two input are low
D.	all input are low
Answer» D. all input are low

5.	The absorption law in Boolean algebra say that
A.	x + x = x
B.	x . y = x
C.	x + x . y = x
D.	none of the above
Answer» C. x + x . y = x

6.	Logic X-OR operation of (4ACO)H & (B53F)H results
A.	aacb
B.	0
C.	abcd
D.	ffff
Answer» D. ffff

7.	What is decimal equivalent of (11011.1000)2 ?
A.	22
B.	22.2
C.	20.2
D.	27.5
Answer» D. 27.5

8.	The negative numbers in the binary system can be represented by
A.	sign magnitude
B.	2\s complement
C.	1\s complement
D.	all of the above
Answer» A. sign magnitude

9.	Negative numbers cannot be represented in
A.	signed magnitude form
B.	1’s complement form
C.	2’s complement form
D.	none of the above
Answer» D. none of the above

10.	*The answer of the operation (10111)2(1110)2 in hex equivalence is**
A.	150
B.	241
C.	142
D.	1.01e+08
Answer» C. 142

11.	The Hexadecimal number equivalent of (4057.06)8 is
A.	82f.027
B.	82f.014
C.	82f.937
D.	83f.014
Answer» B. 82f.014

12.	The NAND gate output will be low if the two inputs are
A.	0
B.	1
C.	10
D.	11
Answer» D. 11

13.	A binary digit is called a
A.	bit
B.	character
C.	number
D.	byte
Answer» A. bit

14.	What is the binary equivalent of the decimal number 368
A.	101110000
B.	110110000
C.	111010000
D.	1.11e+08
Answer» A. 101110000

15.	What is the binary equivalent of the Octal number 367
A.	11110111
B.	11100111
C.	110001101
D.	10111011 1
Answer» A. 11110111

16.	What is the binary equivalent of the Hexadecimal number 368
A.	1111101000
B.	1101101000
C.	1101111000
D.	1.11e+09
Answer» B. 1101101000

17.	What is the binary equivalent of the decimal number 1011
A.	1111110111
B.	1111000111
C.	1111110011
D.	1.11e+09
Answer» C. 1111110011

18.	The gray code equivalent of (1011)2 is
A.	1101
B.	1010
C.	1111
D.	1110
Answer» D. 1110

19.	The decimal equivalent of hex number 1A53 is
A.	6793
B.	6739
C.	6973
D.	6379
Answer» B. 6739

20.	( 734)8 =( )16
A.	c 1 d
B.	d c 1
C.	1 c d
D.	1 d c
Answer» D. 1 d c

21.	The simplification of the Boolean expression (A’BC’)’+ (AB’C)’ is
A.	0
B.	1
C.	a
D.	bc
Answer» B. 1

22.	The hexadecimal number ‘A0’ has the decimal value equivalent to
A.	80
B.	256
C.	100
D.	160
Answer» D. 160

23.	The Boolean expression A.B+ A.B+ A.B is equivalent to
A.	a + b
B.	a\.b
C.	(a + b)\
D.	a.b
Answer» A. a + b

24.	The 2’s complement of the number 1101101 is
A.	101110
B.	111110
C.	110010
D.	10011
Answer» D. 10011

26.	The code where all successive numbers differ from their preceding number by single bit is
A.	binary code.
B.	bcd.
C.	excess – 3.
D.	gray.
Answer» D. gray.

27.	-8 is equal to signed binary number
A.	10001000
B.	oooo1000
C.	10000000
D.	11000000
Answer» A. 10001000

28.	DeMorgan’s first theorem shows the equivalence of
A.	or gate and exclusive or gate.
B.	nor gate and bubbled and gate.
C.	nor gate and nand gate.
D.	nand gate and not gate
Answer» B. nor gate and bubbled and gate.

29.	When signed numbers are used in binary arithmetic, then which one of the following notations would have unique representation for zero.
A.	sign- magnitude.
B.	1’s complement.
C.	2’s complement.
D.	9’s compleme nt.
Answer» A. sign- magnitude.

30.	The decimal equivalent of Binary number 11010 is
A.	26
B.	36
C.	16
D.	23
Answer» A. 26

31.	1’s complement representation of decimal number of -17 by using 8 bit
A.	1110 1110
B.	1101 1101
C.	1100 1100
D.	0001 0001
Answer» A. 1110 1110

32.	The excess 3 code of decimal number 26 is
A.	0100 1001
B.	1011001
C.	1000 1001
D.	1001101
Answer» B. 1011001

33.	How many AND gates are required to realize Y = CD+EF+G
A.	4
B.	5
C.	3
D.	2
Answer» D. 2

34.	The hexadecimal number for (95.5)10 is
A.	(5f.8) 16
B.	(9a.b) 16
C.	( 2e.f) 16
D.	( 5a.4) 16
Answer» A. (5f.8) 16

35.	The octal equivalent of (247) 10 is
A.	( 252) 8
B.	(350) 8
C.	( 367) 8
D.	( 400) 8
Answer» C. ( 367) 8

36.	The number 140 in octal is equivalent to
A.	(96)10 .
B.	( 86) 10
C.	(90) 10 .
D.	none of these.
Answer» A. (96)10 .

37.	The NOR gate output will be low if the two inputs are
A.	11
B.	1
C.	10
D.	all
Answer» D. all

38.	Convert decimal 153 to octal. Equivalent in octal will be
A.	(231)8
B.	( 331) 8
C.	( 431) 8 .
D.	none of these.
Answer» A. (231)8

39.	The decimal equivalent of ( 1100)2 is
A.	12
B.	16
C.	18
D.	20
Answer» A. 12

40.	The binary equivalent of (FA)16 is
A.	1010 1111
B.	1111 1010
C.	10110011
D.	none of these
Answer» B. 1111 1010

41.	How many two-input AND and OR gates are required to realize Y=CD+EF+G
A.	22
B.	23
C.	33
D.	none of these
Answer» A. 22

42.	The excess-3 code of decimal 7 is represented by
A.	1100
B.	1001
C.	1011
D.	1010
Answer» D. 1010

43.	When an input signal A=11001 is applied to a NOT gate serially, its output signal is
A.	111
B.	110
C.	10101
D.	11001
Answer» B. 110

44.	The result of adding hexadecimal number A6 to 3A is
A.	dd
B.	e0
C.	f0
D.	ef
Answer» B. e0

45.	A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate?
A.	or
B.	and
C.	xor
D.	nand
Answer» D. nand

46.	Karnaugh map is used for the purpose of
A.	reducing the electronic circuits used.
B.	to map the given boolean logic function.
C.	to minimize the terms in a boolean expression.
D.	to maximize the terms of a given a boolean expression .
Answer» C. to minimize the terms in a boolean expression.

47.	The 2’s complement of the number 1101110 is
A.	10001
B.	10001
C.	10010
D.	none
Answer» C. 10010

48.	The decimal equivalent of Binary number 10101 is
A.	21
B.	31
C.	26
D.	28
Answer» A. 21

49.	How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB
A.	11
B.	42
C.	32
D.	23
Answer» C. 32

51.	Convert the octal number 7401 to Binary.
A.	1.111e+11
B.	1.1111e+11
C.	1.111e+11
D.	1.11e+11
Answer» A. 1.111e+11

52.	Find the hex sum of (93)16 + (DE)16 .
A.	(171)16
B.	(271)16
C.	(179)16
D.	(181)16
Answer» A. (171)16

53.	Perform 2’s complement subtraction of (7)10 − (11)10 .
A.	1100 (or -4)
B.	1101 (or -5)
C.	1011 (or -3)
D.	1110 (or -6)
Answer» A. 1100 (or -4)

54.	What is the Gray equivalent of (25)10
A.	1101
B.	110101
C.	10110
D.	10101
Answer» D. 10101

55.	Simplify the Boolean expression F = C(B + C)(A + B + C).
A.	c
B.	bc
C.	abc
D.	a+bc
Answer» A. c

56.	Simplify the following expression into sum of products using Karnaugh map F(A,B,C,D) = (1,3,4,5,6,7,9,12,13)
A.	a\b+c\ d+ a\d+bc\
B.	a\b\+c\ d\+ a\d\+b\c\
C.	a\b\+c\ d+ a\d+bc\
D.	a\b+c\ d\+ a\d\+bc\
Answer» A. a\b+c\ d+ a\d+bc\

57.	Simplify F = (ABC)’+( AB)’C+ A’BC’+ A(BC)’+ AB’C.
A.	( a\ + b\ +c\ )
B.	( a\ + b +c )
C.	( a + b +c )
D.	( a + b\ +c\ )
Answer» A. ( a\ + b\ +c\ )

58.	Determine the binary numbers represented by 25.5
A.	11001.1
B.	11011.101
C.	10101.11
D.	11001.010 1
Answer» A. 11001.1

59.	Conversion of decimal number 10.625 into binary number:
A.	1010.101
B.	1110.101
C.	1001.11
D.	1001.101
Answer» A. 1010.101

60.	Conversion of fractional number 0.6875 into its equivalent binary number:
A.	0.1011
B.	0.1111
C.	0.10111
D.	0.0101
Answer» A. 0.1011

61.	Perform the following subtractions using 2’s complement method. 01000 – 01001
A.	1
B.	10
C.	11
D.	11110
Answer» A. 1

62.	Subtraction of 01100-00011 using 2’s complement method. :
A.	1001
B.	1000
C.	1010
D.	110
Answer» A. 1001

63.	Minimize the logic functionY(A,B,C,D) = IZm(0,1,2,3,5,7,8,9,11,14) . Using Karnaugh map.
A.	abc d\ + a\ b\ + b\ c\ + b\ d+ a\d
B.	abc d + a b + b\ c\ + b\ d+ a\d
C.	a\ b\ + b\ c\ + b\ d+ a\d
D.	abc d\ + a\ b\ + b\ c\ + b\ d
Answer» A. abc d\ + a\ b\ + b\ c\ + b\ d+ a\d

64.	Simplify the given expression to its Sum of Products (SOP) form Y = (A + B)(A + (AB)’)C + A'(B+C’)+ A’B+ ABC
A.	ac+ bc+ a\b + a\ c\
B.	ac+ bc+ a\b
C.	bc+ a\b + a\ c\
D.	ac+ a\b + a\ c\
Answer» A. ac+ bc+ a\b + a\ c\

65.	Convert the decimal number 82.67 to its binary, hexadecimal and octal equivalents
A.	(1010010.1010 1011)2; (52.ab)16 ;
B.	(1010010.10 101011)2; (52.ab)16 ;
C.	(1010010.10 101011)2; (52.ab)16 ;
D.	(1010010.
Answer» A. (1010010.1010 1011)2; (52.ab)16 ;

66.	Add 20 and (-15) using 2’s complement.
A.	(100100 )2 or (+4)10
B.	(000100 )2 or (-4)10
C.	both (a) and (b)
D.	none of the above
Answer» A. (100100 )2 or (+4)10

67.	Add 648 and 487 in BCD code.
A.	1135
B.	1136
C.	1235
D.	1138
Answer» A. 1135

68.	(23.6)10 = (X)2 FIND X
A.	(10111.100110 0)2
B.	(10101.1001 100)2
C.	(10001.1001 100)2
D.	(10111.10 00011)2
Answer» A. (10111.100110 0)2

69.	(65.535)10 =(X)16 FIND X
A.	(41.88f5c28)16 .
B.	(42.88f5c28 )16.
C.	(41.88f5c)16.
D.	(42.88f5c )16.
Answer» A. (41.88f5c28)16 .

70.	Convert the decimal number 430 to Excess-3 code:
A.	110110001
B.	110110000
C.	110110011
D.	11010000 1
Answer» A. 110110001

71.	Minimize the following logic function using K-maps F(A,B,C,D) = m(1,3,5,8,9,11,15) + d(2,13)
A.	a b\ c\ + c\ d + b\d + ad
B.	c\ d + b\d + ad
C.	a b\ c\ + b\d + ad
D.	a b\ c\ + c\ d + b\d
Answer» A. a b\ c\ + c\ d + b\d + ad

72.	Convert (2222)10 in Hexadecimal number.
A.	8ae
B.	8be
C.	93c
D.	fff
Answer» A. 8ae

73.	Divide ( 101110) 2 by ( 101)2.
A.	quotient -1001 remainder – 001
B.	quotient – 1000 remainder – 001
C.	quotient – 1001 remainder – 011
D.	quotient – 1001 remainder -000
Answer» A. quotient -1001 remainder – 001

74.	Minimise the logic function (POS Form) F A,B,C,D) = PI M (1, 2, 3, 8, 9, 10, 11,14)× d (7, 15)
A.	f=[(b+d’)+(b+ c’)’(a’+c’)+(a’ +b)]’
B.	f=[(b+d’)+(b +c’)’(‘a’+c’)+ (a’+b)]’
C.	f=[(b+d’)+(b +c’)’(‘a’+c’)+ (a’+b)]’
D.	f=[(b+d’)+ (b+c’)’(‘a’ +c’)+(a’+b )]’
Answer» A. f=[(b+d’)+(b+ c’)’(a’+c’)+(a’ +b)]’

76.	Perform following subtraction(ii) 11011-11001 using 2’s complement
A.	10
B.	111
C.	11
D.	10011
Answer» A. 10

77.	Reduce the following equation using k-map Y = (ABC)’+ A(CD)’+ AB’+ ABCD’+ (AB)’C
A.	b\+(ad)\
B.	b\
C.	(ad)\
D.	b\+ad
Answer» A. b\+(ad)\

78.	Write the expression for Boolean function F (A, B, C) = m (1,4,5,6,7) in standard POS form.
A.	= (a+b+c)(a+b\ +c)(a+b\ +c\ )
B.	= (a+b\ +c)(a+b\ +c\ )
C.	= (a+b+c)(a+b \ +c)
D.	= (a+b+c)(a +b\ +c\ )
Answer» A. = (a+b+c)(a+b\ +c)(a+b\ +c\ )

79.	Convert the decimal number 45678 to its hexadecimal equivalent number.
A.	(b26e)16
B.	(a26e)16
C.	(b26b)16
D.	(b32e)16
Answer» A. (b26e)16

80.	Convert (177.25)10 to octal.
A.	(261.2)8
B.	(260.2)8
C.	(361.2)8
D.	(251.2)8
Answer» A. (261.2)8

81.	Reduce the following equation using k-map Y = B C’ D’+ A’ B C’ D+ A B C’ D+ A’ B C D+ A B C D
A.	bc’ + bd
B.	bc’ + bd+a
C.	bc’ + bd + ac
D.	bc’ + bd + ad
Answer» A. bc’ + bd

82.	8-bit 1’s complement form of –77.25 is
A.	1001101.01
B.	10110010.10 11
C.	01001101.00 10
D.	10110010
Answer» B. 10110010.10 11

83.	In computers, subtraction is generally carried out by
A.	9’s complement
B.	10’s complement
C.	1’s complement
D.	2’s compleme nt
Answer» D. 2’s compleme nt

84.	*The answer of the operation (10111)2(1110)2 in hex equivalence is**
A.	150
B.	241
C.	142
D.	10101111 0
Answer» C. 142

85.	The decimal number equivalent of (4057.06)8 is
A.	2095.75
B.	2095.075
C.	2095.937
D.	2095.094
Answer» D. 2095.094

86.	12-bit 2’s complement of –73.75 is
A.	01001001.110 0
B.	11001001.11 00
C.	10110110.01 00
D.	10110110. 1100
Answer» C. 10110110.01 00

87.	What is decimal equivalent of BCD 11011.1100 ?
A.	22
B.	22.2
C.	20.2
D.	21.2
Answer» B. 22.2

88.	What is the binary equivalent of the decimal number 368
A.	101110000
B.	110110000
C.	111010000
D.	11110000 0
Answer» A. 101110000

89.	(2FAOC)16 is equivalent to
A.	(195 084)10
B.	(001011111 010 0000 1100)2
C.	both (a) and (b)
D.	none of these
Answer» B. (001011111 010 0000 1100)2

90.	The octal equivalent of hexadecimal (A.B)16 is
A.	47.21
B.	12.74
C.	12.71
D.	17.21
Answer» B. 12.74

91.	Logic X-OR operation of (4ACO)H & (B53F)H results
A.	aacb
B.	0
C.	ffff
D.	abcd
Answer» C. ffff

92.	The simplified form of the Boolean expression (X+Y+XY)(X+Z) is
A.	x + y + zx + y
B.	xy – yz
C.	x + yz
D.	xz + y
Answer» C. x + yz

93.	The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either
A.	nand or an xo
B.	or or an xn
C.	o an and or xor
D.	a nor or an xnor
Answer» D. a nor or an xnor

94.	2’s complement of any binary number can be calculated by
A.	adding 1\s complement twice
B.	adding 1 to 1\s complement
C.	subtracting 1 from 1\s complement.
D.	calculating 1\s compleme nt and inverting most significant bit
Answer» B. adding 1 to 1\s complement

95.	Sum-of-Weights method is used
A.	to convert from one number system to other
B.	to encode data
C.	to decode data
D.	to convert from serial to parralel data
Answer» A. to convert from one number system to other

96.	The complement of a variable is always
A.	1
B.	0
C.	inverse
D.	none
Answer» C. inverse

97.	The difference of 111 – 001 equals
A.	100
B.	111
C.	1
D.	110
Answer» D. 110

98.	The Unsigned Binary representation can only represent positive binary numbers
A.	true
B.	false
C.	both (a) and (b)
D.	none of above
Answer» A. true

99.	which of the following rules states that if one input of an AND gate is always 1, the output is equal to the other input?
A.	a +1 =1
B.	a +a =a
C.	a.a = a
D.	a.1= a
Answer» C. a.a = a

101.	Which one of the following is NOT a valid rule of Boolean algebra?
A.	a = a\
B.	aa = a
C.	a + 1 = 1
D.	a + 0 = a
Answer» A. a = a\

102.	In the binary number ‘ 10011 ‘ the weight of the most significant digit is
A.	2^4(2 raise to power 4)
B.	2^3 (2 raise to power 3)
C.	2^0 (2 raise to power 0)
D.	2^1 (2 raise to power 1)
Answer» A. 2^4(2 raise to power 4)

103.	The binary value ‘ 1010110 ‘ is equivalent to decimal
A.	86
B.	87
C.	88
D.	89
Answer» A. 86

104.	2’s complement of hexadecimal number B70A is
A.	b70b
B.	b709
C.	48f6
D.	48f5
Answer» C. 48f6

105.	2’s complement of 5 is
A.	1101
B.	1011
C.	1010
D.	1100
Answer» B. 1011

106.	The 4-bit 2’s complement representation of ‘ -7 ‘ is
A.	111
B.	1111
C.	1001
D.	110
Answer» C. 1001

107.	If we multiply ‘ 723 ‘ and ‘ 34 ‘ by representing them in floating point notation i.e. By first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be
A.	24.582
B.	2.4582
C.	24582
D.	0.24582
Answer» A. 24.582

108.	The output of the expression F=A+B+C will be Logic when A=0, B=1, C=1. the symbol ‘ + ‘ here represents OR Gate.
A.	undefined
B.	one
C.	zero
D.	10 (binary)
Answer» B. one

109.	A NAND gate’s output is LOW if
A.	all inputs are low
B.	all inputs are high
C.	any input is low
D.	any input is high
Answer» C. any input is low

110.	NOR gate is formed by connecting
A.	or gate and then not gate
B.	not gate and then or gate
C.	and gate and then or gate
D.	or gate and then and gate
Answer» C. and gate and then or gate

111.	The AND Gate performs a logical function
A.	addition
B.	subtraction
C.	multiplicatio
D.	division
Answer» C. multiplicatio

112.	The Extended ASCII Code (American Standard Code for Information Interchange) is a code
A.	2-bit
B.	7-bit
C.	8-bit
D.	16-bit
Answer» C. 8-bit

113.	The OR gate performs Boolean .
A.	multiplication
B.	subtraction
C.	division
D.	addition
Answer» D. addition

114.	The output of an AND gate is one when
A.	all of the inputs are one
B.	any of the input is one
C.	any of the input is zero
D.	all the inputs are zero
Answer» A. all of the inputs are one

115.	A NOR’s gate output is HIGH if
A.	all inputs are high
B.	any input is high
C.	any input is low
D.	all inputs are low
Answer» D. all inputs are low

116.	A logic circuit with an output X = A(Bar)BC+AB(Bar) consists of .
A.	two and gates, two or gates, two inverters
B.	three and gates, two or gates, one inverter
C.	two and gates, one or gate, two inverters
D.	two and gates, one or gate
Answer» C. two and gates, one or gate, two inverters

117.	the boolean expression AB’CD’is
A.	a sumterm
B.	a product ter
C.	a literal ter
D.	m always 1
Answer» B. a product ter

118.	The boolean expression X = AB + CD represents
A.	two ors anded together
B.	a 4-input and gate
C.	two ands ored together
D.	an exclusive- or
Answer» C. two ands ored together

119.	The expression is an example of Commutative Law for Multiplication.
A.	ab+c = a+bc
B.	a(b+c) = b(a+c)
C.	ab=ba
D.	a+b=b+a
Answer» C. ab=ba

120.	The total amount of memory that is supported by any digital system depends upon
A.	the organization of memory
B.	the structure of memory
C.	the size of decoding unit
D.	the size of the address bus of the microproc essor
Answer» D. the size of the address bus of the microproc essor

121.	Addition of two octal numbers “36” and “71” results in
A.	213
B.	123
C.	127
D.	345
Answer» C. 127

122.	In which of the following base systems is 123 not a valid number?
A.	base 10
B.	base 16
C.	base8
D.	base 3
Answer» D. base 3

123.	Storage of 1 KB means the following number of bytes
A.	1000
B.	964
C.	1024
D.	1064
Answer» D. 1064

124.	What is the octal equivalent of the binary number: 10111101
A.	675
B.	275
C.	572
D.	573
Answer» B. 275

126.	A NAND gate is called a universal logic element because
A.	it is used by everybody
B.	any logic function can be realized by nand gates alone
C.	all the minization techniques are applicable for optimum nand gate realization
D.	many digital computers use nand gates.
Answer» B. any logic function can be realized by nand gates alone

127.	Digital computers are more widely used as compared to analog computers, because they are
A.	less expensive
B.	always more accurate and faster
C.	useful over wider ranges of problem types
D.	easier to maintain.
Answer» C. useful over wider ranges of problem types

128.	Most of the digital computers do not have floating point hardware because
A.	floating point hardware is costly
B.	it is slower than software
C.	it is not possible to perform floating point addition by hardware
D.	of no specific reason.
Answer» A. floating point hardware is costly

129.	The number 1000 would appear just immediately after
A.	ffff (hex)
B.	1111
C.	7777 (octal)
D.	all of the
Answer» D. all of the

130.	(1(10101)2 is
A.	(37)10
B.	( 69)10
C.	(41 )10
D.	— (5)10
Answer» A. (37)10

131.	The number of Boolean functions that can be generated by n variables is equal to
A.	2n
B.	22 n
C.	2n-1
D.	— 2n
Answer» B. 22 n

132.	Consider the representation of six-bit numbers by two’s complement, one’s complement, or by sign and magnitude: In which representation is there overflow from the addition of the integers 011000 and 011000?
A.	two’s complement only
B.	sign and magnitude and one’s complement only
C.	two’s complement and one’s complement only
D.	all three representa tions.
Answer» D. all three representa tions.

133.	Positive logic in a logic circuit is one in which
A.	logic 0 and 1 are represented by 0 and positive voltage respectively
B.	logic 0 and, – 1 are represented by negative and positive voltages respectively
C.	logic 0 voltage level is higher than logic 1 voltage level
D.	logic 0 voltage level is lower than logic 1 voltage level.
Answer» D. logic 0 voltage level is lower than logic 1 voltage level.

134.	Which of the following gate is a two-level logic gate
A.	or gate
B.	nand gate
C.	exclusive or gate
D.	not gate.
Answer» C. exclusive or gate

135.	An AND gate will function as OR if
A.	all the inputs to the gates are “1”
B.	all the inputs are ‘0’
C.	either of the inputs is “1”
D.	all the inputs and outputs are compleme nted.
Answer» D. all the inputs and outputs are compleme nted.

136.	An OR gate has 6 inputs. The number of input words in its truth table are
A.	6
B.	32
C.	64
D.	128
Answer» C. 64

137.	NAND. gates are preferred over others because these
A.	have lower fabrication area
B.	can be used to make any gate
C.	consume least electronic power
D.	provide maximum density in a chip.
Answer» B. can be used to make any gate

138.	In case of OR gate, no matter what the number of inputs, a
A.	1 at any input causes the
B.	1 at any input causes
C.	0 any input causes the
D.	0 at any input
Answer» A. 1 at any input causes the

139.	Excess-3 code is known as
A.	weighted code
B.	cyclic
C.	self-
D.	algebraic
Answer» C. self-

140.	Indicate which of the following three binary additions are correct? 1.1011 + 1010 = 10101 II. 1010 + 1101 = 10111 III. 1010 + 1101 = 11111
A.	i and ii
B.	ii and iii
C.	iii only
D.	ii and i
Answer» D. ii and i

141.	X – = Y + 1 means
A.	x = x – y + 1
B.	x = –x – y – 1
C.	x = –x + y + 1
D.	x= x – y – 1
Answer» A. x = x – y + 1

142.	A binary digit is called a
A.	bit
B.	byte
C.	number
D.	character
Answer» A. bit

143.	The ASCII code for letter A is
A.	1100011
B.	1111111
C.	1000001
D.	10011
Answer» C. 1000001

144.	Transistor is a
A.	current controlled current device.
B.	current controlled voltage device.
C.	voltage controlled current device.
D.	voltage controlled voltage device.
Answer» A. current controlled current device.

145.	A digital logic device used as a buffer should have what input/output characteristics?
A.	high input impedance and high output impedance
B.	low input impedance and high output impedance
C.	low input impedance and low output impedance
D.	high input impedance and low output impedance
Answer» D. high input impedance and low output impedance

146.	What is the standard TTL noise margin?
A.	5.0 v
B.	0.2 v
C.	0.8 v
D.	0.4 v
Answer» D. 0.4 v

147.	The range of a valid LOW input is:
A.	0.0 v to 0.4 v
B.	0.4 v to 0.8 v
C.	0.0 v to 1.8 v
D.	0.0 v to 2.8 v
Answer» B. 0.4 v to 0.8 v

148.	When an IC has two rows of parallel connecting pins, the device is referred to as:
A.	a qfp
B.	a dip
C.	a phase splitter
D.	cmos
Answer» B. a dip

149.	Which digital IC package type makes the most efficient use of printed circuit board space?
A.	smt
B.	to can
C.	flat pack
D.	dip
Answer» A. smt

151.	Which of the following is the fastest logic
A.	ttl
B.	ecl
C.	cmos
D.	lsi
Answer» B. ecl

152.	The digital logic family which has the lowest propagation delay time is
A.	ecl
B.	ttl
C.	cmos
D.	pmos
Answer» A. ecl

153.	Which TTL logic gate is used for wired ANDing
A.	open collector output
B.	totem pole
C.	tri state output
D.	ecl gates
Answer» A. open collector output

154.	CMOS circuits consume power
A.	equal to ttl
B.	less than ttl
C.	twice of ttl
D.	thrice of ttl
Answer» B. less than ttl

155.	In a positive logic system, logic state 1 corresponds to
A.	positive voltage
B.	higher voltage level
C.	zero voltage level
D.	lower voltage level
Answer» B. higher voltage level

156.	The commercially available 8-input multiplexer integrated circuit in the TTL family is
A.	7495
B.	74153
C.	74154
D.	74151
Answer» B. 74153

157.	The logic 0 level of a CMOS logic device is approximately
A.	1.2 volts
B.	0.4 volts
C.	0volts
D.	5volts
Answer» C. 0volts

158.	Which ofthe following is a universal logic gate?
A.	or
B.	xor
C.	and
D.	nand
Answer» D. nand

159.	How is the noise margin of a logic family defi ned?
A.	voh – vol
B.	greater of vdd – voh and vol – gnd
C.	smaller of vil – vol and voh – vih
D.	vih – vil.
Answer» C. smaller of vil – vol and voh – vih

160.	What parameter causes the main limit on fan-out of CMOS logic in high-speed applications?
A.	d.c. input current
B.	output current
C.	input capacitance
D.	power supply voltage.
Answer» A. d.c. input current

161.	The number of standard loads that the output of the gate can drive with out impairment of its normal operation is
A.	fan-in
B.	fan-out
C.	noise-margin
D.	power- dissipiatio n
Answer» B. fan-out

162.	Measure of power consumed by the gate when fully driven by all its inputs is
A.	fan-in
B.	fan-out
C.	noise-margin
D.	power- dissipiatio n
Answer» D. power- dissipiatio n

163.	Fan-out is specified in terms of
A.	voltage
B.	current
C.	watt
D.	unit load
Answer» D. unit load

164.	Which of the following logic family has highest fan-out
A.	dtl
B.	cmos
C.	rtl
D.	ttl
Answer» B. cmos

165.	Which of following consume minimum power
A.	ttl
B.	rtl
C.	dtl
D.	cmos
Answer» D. cmos

166.	Among the logic families, low power dissipation is in
A.	dtl
B.	cmos
C.	rtl
D.	ttl
Answer» B. cmos

167.	The temperature in which the performance of the IC is effective
A.	operating
B.	fan-out
C.	normal
D.	power-
Answer» A. operating

168.	The nominal value of the dc supply voltage for TTL (transistor-transistor logic) devices is
A.	0v
B.	5v
C.	10v
D.	15v
Answer» B. 5v

169.	The average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns is
A.	propogation delay
B.	fan-out
C.	noise-margin
D.	power- dissipiatio n
Answer» A. propogation delay

170.	the number of inputs connected to the gate without any degradation in the
A.	propogation delay
B.	fan-out
C.	fan- in
D.	power- dissipiatio
Answer» C. fan- in

171.	Which of the following logic gives the complementary outputs?
A.	ecl
B.	ttl
C.	cmos
D.	pmos
Answer» A. ecl

172.	The maximum noise voltage added to an input signal of a digital circuit
A.	fan-in
B.	fan-out
C.	noise-margin
D.	power-
Answer» C. noise-margin

173.	Among the logic families, Slowest logic family is
A.	ttl
B.	rtl
C.	dtl
D.	cmos
Answer» D. cmos

174.	Operating temperature of the IC vary from
A.	0 to70 celsius
B.	0to35celsius
C.	0to 50celsius
D.	0to70celsi
Answer» A. 0 to70 celsius

176.	If the channel is initially doped lightly with p-type impurity a conducting
A.	depletion
B.	enhancemen
C.	both mode
D.	none of
Answer» A. depletion

177.	If the region beneath the gate is left initially uncharged the gate field must induce a channel before current can flow. Thus the gate voltage enhances the channel current and sucha device is said to operate in the
A.	depletion mode operation mos
B.	enhancemen t mode operation of mos
C.	both mode
D.	none of this
Answer» B. enhancemen t mode operation of mos

178.	The n- channel MOS conducts when its
A.	gate- to- source voltage
B.	gate- to- source
C.	gate- to- source
D.	none of this
Answer» A. gate- to- source voltage

179.	The p- channel MOS conducts when its
A.	gate- to-
B.	gate- to-
C.	gate- to-
D.	none of
Answer» C. gate- to-

180.	The fan-out of a MOS-logic gate is higher than that of TTL gates because of its
A.	low input impedance
B.	high input impedance
C.	low output impedance
D.	high output impedance
Answer» D. high output impedance

181.	Which factor does not affect CMOS loading?
A.	charging time associated
B.	discharging time
C.	output capacitance
D.	input capacitanc
Answer» C. output capacitance

182.	Logic gates are the basic elements that make a
A.	analog system
B.	basic system
C.	gating system
D.	digital system
Answer» D. digital system

183.	Which of the following gate is a two-level logic gate
A.	or gate
B.	nand gate
C.	exclusive or gate
D.	not
Answer» C. exclusive or gate

184.	Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit
A.	ttlas
B.	cmos
C.	ecl
D.	ttlls
Answer» C. ecl

185.	The fan Out of a 7400 NAND gate is
A.	2ttl
B.	5ttl
C.	8ttl
D.	10ttl
Answer» D. 10ttl

186.	Which transistor element is used in CMOS logic?
A.	fet
B.	mosfet
C.	bipolar
D.	unijunctio n
Answer» B. mosfet

187.	CMOS circuits are extensively used for ON-chip computers mainly because of their extremely
A.	low power dissipation.
B.	high noise immunity.
C.	large packing density.
D.	low cost.
Answer» C. large packing density.

188.	Which equation is correct?
A.	vnl = vil(max) + vol(max)
B.	vnh = voh(min) + vih(min)
C.	vnl = voh(min) – vih(min)
D.	vnh = voh(min) – vih(min)
Answer» D. vnh = voh(min) – vih(min)

189.	The greater the propagation delay, the
A.	lower the maximum frequency
B.	higher the maximum frequency
C.	maximum frequency is unaffected
D.	minimum frequency is unaffected
Answer» A. lower the maximum frequency

190.	For a CMOS gate, which is the best speed-power product?
A.	1.4 pj
B.	1.6 pj
C.	2.4 pj
D.	3.3 pj
Answer» A. 1.4 pj

191.	In a TTL circuit, if an excessive number of load gate inputs are connected,
A.	voh(min) drops below voh
B.	voh drops below voh(min)
C.	voh exceeds voh(min)
D.	voh and voh(min) are unaffected
Answer» B. voh drops below voh(min)

192.	Which is not a MOSFET terminal?
A.	gate
B.	drain
C.	source
D.	base
Answer» D. base

193.	An open-drain gate is the CMOS counterpart of
A.	an open- collector ttl gate
B.	a tristate ttl gate
C.	a bipolar junction transistor
D.	an emitter- coupled logic gate
Answer» A. an open- collector ttl gate

194.	The active switching element used in all TTL circuits is the
A.	bipolar junction transistor (bjt
B.	field-effect transistor (fet
C.	metal-oxide semiconduct or field- effect transistor (mosfet
D.	unijunctio n transistor (uj)
Answer» A. bipolar junction transistor (bjt

195.	One output structure of a TTL gate is often referred to as a
A.	diode
B.	jbt arrangement
C.	totem-pole arrangement
D.	base, emitter, collector arrangeme nt
Answer» C. totem-pole arrangement

196.	An open-collector output requires
A.	a pull-down resistor
B.	a pull-up resistor
C.	no output resistor
D.	an output resistor
Answer» B. a pull-up resistor

197.	Which is not an output state for tristate logic?
A.	high
B.	low
C.	high-z
D.	low-z
Answer» D. low-z

198.	TTL is alive and well, particularly in
A.	industrial applications
B.	millitary applications
C.	educational applications
D.	commercia lapplicatio ns
Answer» C. educational applications

199.	A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL inputs. How much current does the drive output sink?
A.	–12.8 ma
B.	–8 ma
C.	–1.6 ma
D.	–25.6 ma
Answer» A. –12.8 ma

201.	It is best not to leave unused TTL inputs unconnected (open) because of TTL’s
A.	noise sensitivity
B.	low-current requirement
C.	open- collector outputs
D.	tristate constructi on
Answer» A. noise sensitivity

202.	Which logic family combines the advantages of CMOS and TTL?
A.	bicmos
B.	ttl/cmos
C.	ecl
D.	ttl/mos
Answer» A. bicmos

203.	Which is not part of emitter-coupled logic (ECL)?
A.	differential amplifier
B.	bias circuit
C.	emitter- follower circuit
D.	totem- pole circuit
Answer» D. totem- pole circuit

204.	PMOS and NMOS circuits are used largely in
A.	msi functions
B.	lsi functions
C.	diode functions
D.	ttl functions
Answer» B. lsi functions

205.	The nominal value of the dc supply voltage for TTL and CMOS is
A.	3 v
B.	5 v
C.	10 v
D.	12 v
Answer» B. 5 v

206.	If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is
A.	5.5 mw
B.	5mw
C.	5.5 w
D.	1.1mw
Answer» A. 5.5 mw

207.	The switching speed of CMOS is now
A.	competitive with ttl
B.	three times that of tt
C.	slower than ttl
D.	twice that of ttl
Answer» A. competitive with ttl

208.	One advantage TTL has over CMOS is that TTL is
A.	less expensive
B.	not sensitive to electrostatic discharge
C.	faster
D.	more widely available
Answer» B. not sensitive to electrostatic discharge

209.	TTL operates from a
A.	9-volt suppl
B.	3-volt supply
C.	12-volt supply
D.	5-volt supply
Answer» D. 5-volt supply

210.	A CMOS IC operating from a 3-volt supply will consume
A.	less power than a ttl ic
B.	more power than a ttl ic
C.	the same power as a ttl ic
D.	no power at all
Answer» A. less power than a ttl ic

211.	CMOS IC packages are available in
A.	dip configuration
B.	soic configuration
C.	dip and soic configuration s
D.	none of this
Answer» C. dip and soic configuration s

212.	The terms “low speed” and “high speed,” applied to logic circuits, refer to the
A.	rise time
B.	fall time
C.	propagation delay time
D.	clock speed
Answer» C. propagation delay time

213.	The power dissipation, PD, of a logic gate is the product of the
A.	dc supply voltage and
B.	dc supply voltage and
C.	ac supply voltage and
D.	ac supply voltage
Answer» B. dc supply voltage and

214.	How many different logic level ranges for TTL
A.	1
B.	2
C.	3
D.	4
Answer» D. 4

215.	Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements in
A.	cmos circuits
B.	ttl
C.	ecl circuits
D.	pmos circuits
Answer» A. cmos circuits

216.	ECL IC technology is……………….than TTL technology.
A.	faster
B.	slower
C.	equal
D.	none of this
Answer» A. faster

217.	A major advantage of ECL logic over TTL and CMOS is
A.	low power dissipation
B.	high speed
C.	both low power dissipation and high speed
D.	neither low power dissipation nor high speed
Answer» B. high speed

218.	Digital technologies being used now-a-days are
A.	dtl and emos
B.	ttl, ecl, cmos and rtl
C.	ttl, ecl, cmos and dtl
D.	ttl, ecl, cmos and dtl
Answer» B. ttl, ecl, cmos and rtl

219.	Which of the following is the fastest logic
A.	ttl
B.	ecl
C.	cmos
D.	pmos
Answer» B. ecl

220.	CMOS circuits are extensively used for ON-chip computers mainly because of their extremely
A.	low power dissipation
B.	high noise immunity
C.	large packing density
D.	low cost.
Answer» C. large packing density

221.	The MSI chip 7474 is
A.	dual edge triggered jk flip-flop (ttl).
B.	dual edge triggered d flip-flop (cmos).
C.	dual edge triggered d flip-flop (ttl).
D.	dual edge triggered jk flip-flop (cmos).
Answer» C. dual edge triggered d flip-flop (ttl).

222.	The logic 0 level of a CMOS logic device is approximately
A.	1.2 volts
B.	0.4 volts
C.	5 volts
D.	0 volts
Answer» D. 0 volts

223.	What is unique about TTL devices such as the 74SXX?
A.	these devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn-on and turn-off times, which translates into higher frequency operation.
B.	the gate transistors are silicon (s), and the gates therefore have lower values of leakage current.
C.	the s denotes the fact that a single gate is present in the ic rather than the usual package of 2–6 gates.
D.	the s denotes a slow version of the device, which is a consequen ce of its higher power rating.
Answer» A. these devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn-on and turn-off times, which translates into higher frequency operation.

224.	Which of the following logic families has the shortest propagation delay?
A.	cmos
B.	bicmos
C.	ecl
D.	74sxx
Answer» C. ecl

226.	What should be done to unused inputs on TTL gates?
A.	they should be left disconnected so as not to produce a load on any of the other circuits and to minimize power loading on the voltage source.
B.	all unused gates should be connected together and tied to v through a 1 k resistor.
C.	all unused inputs should be connected to an unused output; this will ensure compatible loading on both the unused inputs and unused outputs.
D.	unused and and nand inputs should be tied to vcc through a 1 k resistor; unused or and nor inputs should be grounded.
Answer» D. unused and and nand inputs should be tied to vcc through a 1 k resistor; unused or and nor inputs should be grounded.

227.	Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the chip?
A.	50 mw
B.	82.5 mw
C.	115 mw
D.	165 mw
Answer» B. 82.5 mw

228.	Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate?
A.	yes
B.	no
Answer» A. yes

229.	What is the major advantage of ECL logic?
A.	very high speed
B.	wide range of operating voltage
C.	very low cost
D.	very high power
Answer» A. very high speed

230.	As a general rule, the lower the value of the speed–power product, the better the device because of its:
A.	long propagation delay and high power consumption
B.	long propagation delay and low power consumption
C.	both
D.	none of above
Answer» B. long propagation delay and low power consumption

231.	What is the difference between the 54XX and 74XX series of TTL logic gates?
A.	54xx is faster.
B.	54xx is slower.
C.	54xx has a wider power supply and expanded temperature range.
D.	54xx has a narrower power supply and contracted temperatu re range.
Answer» C. 54xx has a wider power supply and expanded temperature range.

232.	What is the range of invalid TTL output voltage?
A.	0.0–0.4 v
B.	0.4–2.4 v
C.	2.4–5.0 v
D.	0.0–5.0 v
Answer» B. 0.4–2.4 v

233.	An open collector output can current, but it cannot .
A.	sink, source current
B.	source, sink current
C.	sink, source voltage
D.	source, sink voltage
Answer» A. sink, source current

234.	Why is a decoupling capacitor needed for TTL ICs and where should it be connected
A.	to block dc, connect to input pins
B.	to reduce noise, connect to input pins
C.	to reduce the effects of noise, connect between power supply and ground
D.	none of above
Answer» C. to reduce the effects of noise, connect between power supply and ground

235.	Which of the following summarizes the important features of emitter- coupled logic (ECL)?
A.	low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption
B.	good noise immunity, negative logic, high- frequency capability, low power dissipation, and short propagation time
C.	low propagation time, high- frequency response, low power consumption, and high output voltage swings
D.	poor noise immunity, positive supply voltage operation, good low- frequency operation, and low power
Answer» A. low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption

236.	Why is a pull-up resistor needed for an open collector gate?
A.	to provide vcc for the ic
B.	to provide ground for the ic
C.	to provide the high voltage
D.	to provide the low voltage
Answer» C. to provide the high voltage

237.	Why is a pull-up resistor needed when connecting TTL logic to CMOS logic?
A.	to increase the output low voltage
B.	to decrease the output low voltage
C.	to increase the output high voltage
D.	to decrease the output high voltage
Answer» C. to increase the output high voltage

238.	The word “interfacing” as applied to digital electronics usually means:
A.	a conditioning circuit connected between a standard ttl nand gate and a standard ttl or gate
B.	a circuit connected between the driver and load to condition a signal so that it is compatible with the load
C.	any gate that is a ttl operational amplifier designed to condition signals between nmos transistors
D.	any ttl circuit that is an input buffer stage
Answer» B. a circuit connected between the driver and load to condition a signal so that it is compatible with the load

239.	The rise time (tr) is the time it takes for a pulse to rise from its point up to its point. The fall time (tf) is the length of time it takes to fall from the to the point.
A.	10%, 90%, 90%, 10%
B.	90%, 10%, 10%, 90%
C.	20%, 80%, 80%, 20%
D.	10%, 70.7%, 70.7%, 10%
Answer» A. 10%, 90%, 90%, 10%

240.	The term buffer/driver signifies the ability to provide low output currents to drive light loads.
A.	true
B.	false
Answer» B. false

241.	PMOS and NMOS .
A.	represent mosfet devices utilizing either p-channel or n- channel devices exclusively within a given gate
B.	are enhancement -type cmos devices used to produce a series of high-speed logic known as 74hc
C.	represent positive and negative mos-type devices, which can be operated from differential power supplies and are compatible with operational amplifiers
D.	none of the above
Answer» A. represent mosfet devices utilizing either p-channel or n- channel devices exclusively within a given gate

242.	Why is the operating frequency for CMOS devices critical for determining power dissipation?
A.	at low frequencies, at low frequencies, power dissipation increases.
B.	at high frequencies, the gate will only be able to deliver 70.7 % of rated power.
C.	at high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.
D.	at high frequencie s, the gate will only be able to deliver 70.7 % of rated power and charging and dischargin g the gate capacitanc e will draw a heavy current from the power supply and thus increase power dissipation .
Answer» C. at high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.

243.	Ten TTL loads per TTL driver is known as:
A.	noise immunity
B.	fan-out
C.	power dissipation
D.	propagatio n delay
Answer» B. fan-out

244.	The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of:
A.	a cmos inverting bilateral switch between the stages
B.	a ttl tristate inverting buffer between the stages
C.	a cmos noninverting bilateral switch between the stages
D.	a cmos buffer or inverting buffer
Answer» D. a cmos buffer or inverting buffer

245.	Totem-pole outputs be connected because .
A.	can, in parallel, sometimes higher current is required
B.	cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices
C.	should, in series, certain applications may require higher output voltage
D.	can, together, together they can handle larger load currents and higher output voltages
Answer» B. cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices

246.	The high input impedance of MOSFETs:
A.	allows faster switching
B.	reduces input current and power dissipation
C.	prevents dense packing
D.	creates low-noise reactions
Answer» B. reduces input current and power dissipation

247.	The output current capability of a single 7400 NAND gate when HIGH is called
A.	source current
B.	sink current
C.	ioh
D.	source current of ioh
Answer» A. source current

248.	The time needed for an output to change from the result of an input change is known as:
A.	noise immunity
B.	fan-out
C.	propagation delay
D.	rise time
Answer» C. propagation delay

249.	The problem of interfacing IC logic families that have different supply voltages (VCC’s) can be solved by using a:
A.	level-shifter
B.	tristate shifter
C.	decoupling capacitor
D.	pull-down resistor
Answer» A. level-shifter

251.	When is a level-shifter circuit needed in interfacing logic?
A.	a level shifter is always needed.
B.	a level shifter is never needed.
C.	when the supply voltages are the same
D.	when the supply voltages are different
Answer» D. when the supply voltages are different

252.	A TTL totem-pole circuit is designed so that the output transistors:
A.	are always on together
B.	provide linear phase splitting
C.	provide voltage regulation
D.	are never on together
Answer» D. are never on together

253.	The most common TTL series ICs are:
A.	e-mosfet
B.	7400
C.	quad
D.	ac00
Answer» B. 7400

254.	Which family of devices has the characteristic of preventing saturation during operation?
A.	ttl
B.	ecl
C.	mos
D.	iil
Answer» B. ecl

255.	How many 74LSTTL logic gates can be driven from a 74TTL gate?
A.	10
B.	20
C.	30
D.	40
Answer» B. 20

256.	What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?
A.	the hct series is faster.
B.	the hct series is slower.
C.	he hct series is input and output voltage compatible with ttl.
D.	the hct series is not input and output voltage compatible with ttl.
Answer» C. he hct series is input and output voltage compatible with ttl.

257.	Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?
A.	these are worst-case conditions.
B.	these are normal conditions.
C.	these are best-case conditions.
D.	it doesn\t matter what values are used.
Answer» A. these are worst-case conditions.

258.	What is the standard TTL noise margin?
A.	5.0 v
B.	0.0 v
C.	0.8 v
D.	0.4 v
Answer» D. 0.4 v

259.	Which logic family is characterized by a multiemitter transistor on the input?
A.	ecl
B.	cmos
C.	ttl
D.	none of the above
Answer» C. ttl

260.	he problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by:
A.	adding a fixed voltage- divider bias resistive network at the output of the ttl device
B.	avoiding this condition and only using ttl to drive ttl
C.	adding an external pull- down resistor to ground
D.	adding an external pull-up resistor to vcc
Answer» D. adding an external pull-up resistor to vcc

261.	How does the 4000 series of CMOS logic compare in terms of speed and power dissipation to the standard family of TTL logic?
A.	more power dissipation and slower speed
B.	more power dissipation and faster speed
C.	less power dissipation and faster speed
D.	less power dissipation and slower speed
Answer» D. less power dissipation and slower speed

262.	What should be done with unused inputs to a TTL NAND gate?
A.	let them float
B.	tie them low
C.	tie them high
D.	none of the above
Answer» C. tie them high

263.	Which of the following logic families has the highest maximum clock frequency?
A.	s-ttl
B.	as-ttl
C.	hs-ttl
D.	hcmos
Answer» B. as-ttl

264.	Why is the fan-out of CMOS gates frequency dependent?
A.	each cmos input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a cmos gate.
B.	when the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal; this defines the upper operating frequency.
C.	the higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
D.	the input gates of the fets are predomina ntly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate.
Answer» D. the input gates of the fets are predomina ntly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate.

265.	What must be done to interface TTL to CMOS?
A.	a dropping resistor must be used on the cmos 12 v supply to reduce it to 5 v for the ttl.
B.	as long as the cmos supply voltage is 5 v, they can be interfaced; however, the fan-out of the ttl is limited to five cmos gates.
C.	a 5 v zener diode must be placed across the inputs of the ttl gates in order to protect them from the higher output voltages of the cmos gates.
D.	a pull-up resistor must be used between the ttl output- cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node.
Answer» D. a pull-up resistor must be used between the ttl output- cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node.

266.	What causes low-power Schottky TTL to use less power than the 74XX series TTL?
A.	the schottky- clamped transistor
B.	nothing. the 74xx series uses less power.
C.	a larger value resistor
D.	using nand gates
Answer» C. a larger value resistor

267.	What are the major differences between the 5400 and 7400 series of ICs?
A.	the 5400 series are military grade and require tighter supply voltages and temperatures.
B.	the 5400 series are military grade and allow for a wider range of supply voltages and temperature s.
C.	the 7400 series are an improvement over the original 5400s.
D.	the 7400 series was originally developed by texas instrumen ts. the 5400 series was brought out by national semicondu ctors after ti\s patents expired, as a second supply source.
Answer» B. the 5400 series are military grade and allow for a wider range of supply voltages and temperature s.

268.	Which of the following statements apply to CMOS devices?
A.	the devices should not be inserted into circuits with the power on.
B.	all tools, test equipment, and metal workbenches should be tied to earth ground.
C.	the devices should be stored and shipped in antistatic tubes or conductive foam.
D.	all of the above.
Answer» D. all of the above.

269.	Which of the logic families listed below allows the highest operating frequency?
A.	74as
B.	ecl
C.	hcmos
D.	54s
Answer» B. ecl

270.	What is the increase in switching speed between 74LS series TTL and 74HC/HCT (High-Speed CMOS)?
A.	5
B.	10
C.	50
D.	100
Answer» B. 10

271.	What does ECL stand for?
A.	electron- coupled logic;
B.	emitter- coupled logic;
C.	energy- coupled logic;
D.	none of above
Answer» B. emitter- coupled logic;

272.	What is unique about TTL devices such as the 74S00?
A.	the gate transistors are silicon (s), and the gates therefore have lower values of leakage current.
B.	the s denotes the fact that a single gate is present in the ic rather than the usual package of 2–6 gates.
C.	the s denotes a slow version of the device, which is a consequence of its higher power rating.
D.	the devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn on and turn off times, which translates into higher frequency operation.
Answer» D. the devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn on and turn off times, which translates into higher frequency operation.

273.	he bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is:
A.	emitter- coupled logic (ecl).
B.	current- mode logic (cml).
C.	transistor- transistor logic (ttl).
D.	emitter- coupled logic (ecl) and transistor- transistor logic (ttl).
Answer» D. emitter- coupled logic (ecl) and transistor- transistor logic (ttl).

274.	In TTL the noise margin is between
A.	0.4 v and 0.8 v.
B.	0.0 v and 0.4 v.
C.	0.0 v and 0.5 v.
D.	0.0v and 0.8 v.
Answer» A. 0.4 v and 0.8 v.

276.	The highest noise margin is offered by
A.	cmos
B.	ttl
C.	ecl
D.	bicmos
Answer» B. ttl

277.	What is the transitive voltage for the voltage input of a CMOS operating from 10V supply ?
A.	1v
B.	5v
C.	10v
D.	20v
Answer» B. 5v

278.	Which of the following logic families is well suited for high-speed operations ?
A.	ttl
B.	ecl
C.	mos
D.	cmos
Answer» B. ecl

279.	Which of the following is the fastest logic?
A.	ecl
B.	ttl
C.	mos
D.	cmos
Answer» A. ecl

280.	he digital logic family which has the lowest propagation delay time is
A.	ecl
B.	ttl
C.	cmos
D.	pmos
Answer» C. cmos

281.	Which of the following statements is wrong ?
A.	propagation delay is the time required for a gate to change its state
B.	noise immunity is the amount of noise which can be applied to the input of a gate without causing the gate to change state
C.	fan-in of a gate is always equal to fan-out of the same gate
D.	operating speed is the maximum frequency at which digital data can be applied to a gate
Answer» C. fan-in of a gate is always equal to fan-out of the same gate

282.	Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ?
A.	function table
B.	truth table
C.	routing table
D.	ascii table
Answer» B. truth table

283.	The digital logic family which has minimum power dissipation is
A.	ttl
B.	ecl
C.	mos
D.	cmos
Answer» D. cmos

284.	In the following question, match each of the items A, B and C on the left with an approximation item on the right A. Shift register can be used 1. for code conversion B. A multiplexer can be used 2. to generate memory slipto select C. A decoder can be used 3. for parallel to serial conversion 4. as many to one switch 5. for analog to digital conversion
A.	a b c 1 2 3
B.	a b c 3 4 1
C.	a b c 5 4 2
D.	a b c 1 3 5
Answer» B. a b c 3 4 1

285.	A standard SOP form has terms that have all the variables in the domain of the expression.
A.	sum
B.	sub
C.	mult
D.	div
Answer» A. sum

286.	How many data select lines are required for selecting eight inputs?
A.	1
B.	2
C.	3
D.	4
Answer» C. 3

287.	Half adder circuit is ?
A.	half of an and gate
B.	a circuit to add two bits together
C.	half of a nand gate
D.	none of above
Answer» B. a circuit to add two bits together

288.	The full adder adds the Kth bits of two numbers to the
A.	difference of the previous bits
B.	sum of all previous bits
C.	carry from ( k – 1 )th bit
D.	sum of previous bit
Answer» C. carry from ( k – 1 )th bit

289.	The number of two input multiplexers required to construct a 210 input multiplexer is,
A.	31
B.	10
C.	127
D.	1023
Answer» D. 1023

290.	A small dot or circle printed on top of an IC indicates
A.	vcc
B.	gnd
C.	pin 14
D.	pin 1
Answer» D. pin 1

291.	Which of the following adders can add three or more numbers at a time ?
A.	parallel adder
B.	carry-look- ahead adder
C.	carry-save- adder d.
D.	full adder
Answer» B. carry-look- ahead adder

292.	An AND circuit
A.	is a memory circuit
B.	gives an output when all input signals are present simultaneous ly
C.	is a -ve or gate
D.	is a linear circuit
Answer» B. gives an output when all input signals are present simultaneous ly

293.	What are the three output conditions of a three-state buffer?
A.	high, low, float
B.	1, 0, float
C.	both of the above
D.	neither of the above
Answer» C. both of the above

294.	The device which changes from serial data to parallel data is
A.	counter
B.	multiplexe r
C.	demultiple xer
D.	flip-flop
Answer» C. demultiple xer

295.	A device which converts BCD to Seven Segment is called
A.	multiplexer
B.	demultipl exer
C.	encoder
D.	decoder
Answer» D. decoder

296.	How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
A.	1
B.	2
C.	4
D.	8
Answer» C. 4

297.	A device which converts BCD to Seven Segment is called
A.	encoder
B.	decoder
C.	multiplexer
D.	demultiple xer
Answer» B. decoder

298.	A multiplexer is a logic circuit that
A.	accepts one input and gives several output
B.	accepts many inputs and gives many output
C.	accepts many inputs and gives one output
D.	accepts one input and gives one output
Answer» C. accepts many inputs and gives one output

299.	In order to implement a n variable switching function, a MUX must have
A.	2n inputs
B.	2n+1 inputs
C.	2n-1 inputs
D.	2n-1 inputs
Answer» A. 2n inputs

301.	A combinational logic circuit which sends data coming from a single source to two or more separate destinations is
A.	decoder
B.	encoder
C.	multiplexer
D.	demultiple xer
Answer» D. demultiple xer

302.	Data can be changed from special code to temporal code by using
A.	shift registers
B.	counters
C.	combination al circuits
D.	a/d converters
Answer» A. shift registers

303.	Odd parity of word can beconveniently tested by
A.	or gate
B.	and gate
C.	nor gate
D.	xor gate
Answer» D. xor gate

304.	Which one of the following will give the sum of full adders as output ?
A.	three point majority circuit
B.	three bit parity checker
C.	three bit comparator
D.	three bit counter
Answer» D. three bit counter

305.	The number of full and half-adders required to add 16-bit numbers is
A.	8 half-adders, 8 full-adders
B.	1 half-adder, 15 full- adders
C.	16 half- adders, 0 full- adders
D.	4 half- adders, 12 full-adders
Answer» B. 1 half-adder, 15 full- adders

306.	A one-to-four line demultiplexer is to be implemented using a memory. How many bits must each word have ?
A.	1 bit
B.	2 bits
C.	4 bits
D.	8 bits
Answer» A. 1 bit

307.	What logic function is produced by adding an inverter to the output of an AND gate ?
A.	nand
B.	nor
C.	xor
D.	or
Answer» A. nand

308.	A demultiplexer is used to
A.	route the data from single input to one of many outputs
B.	select data from several inputs and route it to single output
C.	perform serial to parallel conversion
D.	all of these
Answer» A. route the data from single input to one of many outputs

309.	How many full adders are required to construct an m-bit parallel adder ?
A.	m/2
B.	m-1
C.	m
D.	m+1
Answer» B. m-1

310.	Parallel adders are
A.	combinational logic circuits
B.	sequential logic circuits
C.	both (a) and (b)
D.	none of these
Answer» B. sequential logic circuits

311.	The digital multiplexer is basically a combination logic circuit to perform the operation
A.	and-and
B.	or-or
C.	and-or
D.	or-and
Answer» C. and-or

312.	How many lines the truth table for a four-input NOR gate would contain to cover all possible input combinations ?
A.	4
B.	8
C.	12
D.	16
Answer» D. 16

313.	How many truth tables can be made from one function table ?
A.	1
B.	2
C.	3
D.	any no
Answer» B. 2

314.	A comparison between serial and parallel adder reveals that serial order
A.	is slower
B.	is faster
C.	operates at the same speed as parallel adder
D.	is more complicate d
Answer» A. is slower

315.	What is the largest number of data inputs which a data selector with two control inputs can have ?
A.	2
B.	4
C.	6
D.	8
Answer» B. 4

316.	If a logic gates has four inputs, then total number of possible input combinations is
A.	4
B.	8
C.	16
D.	32
Answer» C. 16

317.	If a logic gates has four inputs, then total number of possible input combinations is
A.	input combination at the time
B.	input combination and the previous output
C.	nput combination at that time and the previous input combination
D.	present output and the previous output
Answer» A. input combination at the time

318.	A combinational logic circuit which generates a particular binary word or number is
A.	decoder
B.	multiplexer
C.	encoder
D.	demultiple xer
Answer» A. decoder

319.	Which of the following circuit can be used as parallel to serial converter ?
A.	multiplexer
B.	demultiplexe r
C.	decoder
D.	digital counter
Answer» A. multiplexer

320.	In which of the following adder circuits, the carry look ripple delay is eliminated ?
A.	half adder
B.	full adder
C.	parallel adder
D.	carry- look- ahead adder
Answer» C. parallel adder

321.	Adders
A.	adds 2 bits
B.	is called so because a full adder involves two half-adders
C.	needs two input and generates two output
D.	all of these
Answer» D. all of these

322.	Excess-3 code is known as
A.	weighted code
B.	cyclic redundancy code
C.	self- complementi ng code
D.	algebraic code.
Answer» C. self- complementi ng code

323.	The number of control lines for 32 to 1 multiplexer is
A.	4
B.	16
C.	5
D.	6
Answer» C. 5

324.	The selector inputs to an arithmetic-logic unit (ALU) determine the:
A.	selection of
B.	arithmetic
C.	data word
D.	clock
Answer» B. arithmetic

326.	The inverter OR-gate and AND gate are called deeision-making elements because they can recognize some input while disregarding others. A gate
A.	words,high
B.	bytes,low
C.	bytes,high
D.	character,l ow
Answer» A. words,high

327.	Which one of the following set of gates are best suited for ‘parity’ checking and ‘parity’ generation.
A.	and, or, not gates
B.	ex-nor or ex-or gates
C.	nand gates
D.	nor gates
Answer» B. ex-nor or ex-or gates

328.	How many inputs are required for a 1-of-10 BCD decoder?
A.	4
B.	8
C.	10
D.	1
Answer» A. 4

329.	Most demultiplexers facilitate which of the following?
A.	decimal to hexadecimal
B.	single input, multiple outputs
C.	ac to dc
D.	odd parity to even parity
Answer» B. single input, multiple outputs

330.	One application of a digital multiplexer is to facilitate:
A.	code conversion
B.	parity checking
C.	parallel-to- serial data conversion
D.	data generation
Answer» C. parallel-to- serial data conversion

331.	Select one of the following statements that best describes the parity method of error detection:
A.	best suited for detecting single-bit errors in transmitted codes.
B.	best suited for detecting double-bit errors that occur during the transmission of codes from one location to another.
C.	a and b
D.	none of the above
Answer» A. best suited for detecting single-bit errors in transmitted codes.

332.	A multiplexed display:
A.	accepts data inputs from one line and passes this data to multiple output lines
B.	uses one display to present two or more pieces of information
C.	accepts data inputs from multiple lines and passes this data to multiple output lines
D.	accepts data inputs from several lines and multiplexe s this input data to four bcd lines
Answer» B. uses one display to present two or more pieces of information

333.	In which of the following gates, the output is 1, if and only if at least one input is 1?
A.	nor
B.	and
C.	or
D.	nand
Answer» C. or

334.	The time required for a gate or inverter to change its state is called
A.	rise time iz
B.	decay time
C.	propagation time
D.	charging time
Answer» C. propagation time

335.	The time required for a pulse to change from 10 to 90 percent of its maximum value is called
A.	rise time iz
B.	decay time
C.	propagation time
D.	operating speed
Answer» A. rise time iz

336.	The maximum frequency at which digital data can be applied to gate is called
A.	operating speed
B.	propagation speed
C.	binary level transaction period
D.	charging time
Answer» A. operating speed

337.	What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ?
A.	one
B.	two
C.	three
D.	four
Answer» C. three

338.	The time required for a pulse to decrease from 90 to 10 per cent of its maximum value is called
A.	rise time
B.	decay time
C.	binary level transition period
D.	propagatio n delay
Answer» B. decay time

339.	Which of the following gates would output 1 when one input is 1 and other input is 0 ?
A.	or gate
B.	and gate
C.	nand gate
D.	and gate
Answer» D. and gate

340.	Which of the following expressions is not equivalent to X ‘ ?
A.	x nand x
B.	x nor x
C.	x nand 1
D.	x nor 1
Answer» D. x nor 1

341.	Which of the following gates are added to the inputs of the OR gate to convert it to the NAND gate ?
A.	not
B.	and
C.	or
D.	xor
Answer» A. not

342.	The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ?
A.	or gate
B.	and
C.	nand
D.	xor
Answer» D. xor

343.	Which of the following gates is known as coincidence detector ?
A.	and gate
B.	or gate
C.	not gate
D.	nand gate
Answer» A. and gate

344.	Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ?
A.	function table
B.	truth table
C.	routing table
D.	ascii table
Answer» B. truth table

345.	A positive AND gate is also a negative
A.	nand gate
B.	nor gate
C.	and gate
D.	or gate
Answer» D. or gate

346.	An OR gate can be imagined as
A.	switches connected in series
B.	switches connected in parallel
C.	mos transistors connected in series
D.	none of these
Answer» B. switches connected in parallel

347.	Which combination of gates does not allow the implementation of an arbitrary boolean function?
A.	or gates and and gates only
B.	or gates and exclusive or gate only
C.	or gates and not gates only
D.	nand gates only
Answer» A. or gates and and gates only

348.	The output of NOR gate is
A.	high if all of its inputs are high
B.	low if all of its inputs are low
C.	high if all of its inputs are low
D.	high if only of its inputs is low
Answer» C. high if all of its inputs are low

349.	A toggle operation cannot be performed using a single
A.	nor gate
B.	and gate
C.	nand gate
D.	xor gate
Answer» B. and gate

351.	What is the minimum number of 2 input NAND gates required to implement the function F = (x’+y’) (z+w)
A.	6
B.	5
C.	4
D.	3
Answer» C. 4

352.	How many truth tables can be made from one function table ?
A.	one
B.	two
C.	three
D.	any numbers
Answer» B. two

353.	What is the largest number of data inputs which a data selector with two control inputs can have ?
A.	2
B.	4
C.	8
D.	16
Answer» B. 4

354.	A combinational circuit is one in which the output depends on the
A.	input combination at the time
B.	input combination and the previous output
C.	input combination at that time and the previous input combination
D.	present output and the previous output
Answer» A. input combination at the time

355.	The function of a multiplexer is
A.	to decode information
B.	to select 1 out of n input data sources and to transmit it to single channel
C.	to transit data on n lines
D.	to perform serial to parallel conversion
Answer» B. to select 1 out of n input data sources and to transmit it to single channel

356.	For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. What is the status of the Y output?
A.	low
B.	high
C.	don\t care
D.	cannot be determine d
Answer» A. low

357.	Convert BCD 0001 0010 0110 to binary.
A.	1111110
B.	1111000
C.	1111101
D.	1111111
Answer» A. 1111110

358.	Convert BCD 0001 0111 to binary.
A.	10101
B.	10001
C.	10010
D.	11000
Answer» C. 10010

359.	How many 1-of-16 decoders are required for decoding a 7-bit binary number?
A.	5
B.	6
C.	7
D.	8
Answer» D. 8

360.	The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.)
A.	and/or
B.	nand
C.	nor
D.	or/and
Answer» B. nand

361.	Which of the following statements accurately represents the two BEST methods of logic circuit simplification?
A.	boolean algebra and karnaugh mapping
B.	karnaugh mapping and circuit waveform analysis
C.	actual circuit trial and error evaluation and waveform analysis
D.	boolean algebra and actual circuit trial and error evaluation
Answer» A. boolean algebra and karnaugh mapping

362.	Which of the following combinations cannot be combined into K-map groups?
A.	corners in the same row
B.	corners in the same column
C.	diagonal corners
D.	overlappin g combinati ons
Answer» C. diagonal corners

363.	As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the possible faults listed, select the one that most probably is causing the problem.
A.	a defective ic chip that is drawing excessive current from the power supply
B.	a solar bridge between the inputs on the first ic chip on the board
C.	an open input on the first ic chip on the board
D.	a defective output ic chip that has an internal open to v cc
Answer» C. an open input on the first ic chip on the board

364.	Which gate is best used as a basic comparator?
A.	nor
B.	or
C.	exclusive-or
D.	and
Answer» C. exclusive-or

365.	The device shown here is most likely a .
A.	comparator
B.	multiplexer
C.	demultiplexe r
D.	parity generator
Answer» C. demultiplexe r

366.	For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs?
A.	all are high.
B.	all are low.
C.	all but are low.
D.	all but are high.
Answer» A. all are high.

367.	In VHDL, macrofunctions is/are:
A.	digital circuits.
B.	analog circuits.
C.	a set of bit vectors.
D.	preprogra mmed ttl devices.
Answer» D. preprogra mmed ttl devices.

368.	Which of the following expressions is in the product-of-sums form?
A.	(a + b )(c + d )
B.	(ab )(cd )
C.	ab (cd )
D.	ab + cd
Answer» A. (a + b )(c + d )

369.	Which of the following is an important feature of the sum-of-products form of expressions?
A.	all logic circuits are reduced to nothing more than simple and and or operations.
B.	the delay times are greatly reduced over other forms.
C.	no signal must pass through more than two gates, not including inverters.
D.	the maximum number of gates that any signal must pass through is reduced by a factor of two.
Answer» A. all logic circuits are reduced to nothing more than simple and and or operations.

370.	An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help isolate the problem?
A.	current tracer
B.	logic probe
C.	oscilloscope
D.	logic analyzer
Answer» A. current tracer

371.	The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
A.	a > b = 1, a < b = 0, a < b = 1
B.	a > b = 0, a < b = 1, a = b = 0
C.	a > b = 1, a < b = 0, a = b = 0
D.	a > b = 0, a < b = 1, a = b = 1
Answer» C. a > b = 1, a < b = 0, a = b = 0

372.	A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?
A.	the output of the gate appears to be open.
B.	the dim indication on the logic probe indicates that the supply voltage is probably low.
C.	the dim indication is a result of a bad ground connection on the logic probe.
D.	the gate may be a tristate device.
Answer» A. the output of the gate appears to be open.

373.	Each “1” entry in a K-map square represents:
A.	a high for each input truth table condition that produces a high output.
B.	a high output on the truth table for all low input combination s.
C.	a low output for all possible high input conditions.
D.	a don\t care condition for all possible input truth table combinati ons.
Answer» A. a high for each input truth table condition that produces a high output.

374.	Looping on a K-map always results in the elimination of:
A.	variables within the loop that appear only in their complemented form.
B.	variables that remain unchanged within the loop.
C.	variables within the loop that appear in both complemente d and uncompleme nted form.
D.	variables within the loop that appear only in their uncomple mented form.
Answer» C. variables within the loop that appear in both complemente d and uncompleme nted form.

376.		What is the indication of a short on the input of a load gate?
A.		only the output of the defective gate is affected.
B.		there is a signal loss to all gates on the node.
C.		the affected node will be stuck in the low state.
D.		there is a signal loss to all gates on the node, and the affected node will be stuck in the low state.
Answer» D. there is a signal loss to all gates on the node, and the affected node will be stuck in the low state.

377.	In HDL, LITERALS is/are:
A.	digital systems.
B.	scalars.
C.	binary coded decimals.
D.	a numbering system.
Answer» B. scalars.

378.	Which of the following expressions is in the sum-of-products form?
A.	(a + b )(c + d )
B.	(ab )(cd )
C.	ab (cd )
D.	ab + cd
Answer» D. ab + cd

379.	The carry propagation can be expressed as .
A.	cp = ab
B.	cp = a + b
D.
Answer» B. cp = a + b

380.	A decoder can be used as a demultiplexer by .
A.	tying all enable pins low
B.	tying all data-select lines low
C.	tying all data- select lines high
D.	using the input lines for data selection and an enable line for data input
Answer» D. using the input lines for data selection and an enable line for data input

381.	How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010?
A.	1
B.	2
C.	3
D.	4
Answer» C. 3

382.	Which statement below best describes a Karnaugh map?
A.	a karnaugh map can be used to replace boolean rules.
B.	the karnaugh map eliminates the need for using nand and nor gates.
C.	variable complements can be eliminated by using karnaugh maps.
D.	karnaugh maps provide a visual approach to simplifyin g boolean expression s.
Answer» D. karnaugh maps provide a visual approach to simplifyin g boolean expression s.

383.	A certain BCD-to-decimal decoder has active-HIGH inputs and active- LOW outputs. Which output goes LOW when the inputs are 1001?
A.	0
B.	3
C.	9
D.	none. all outputs are high.
Answer» C. 9

384.	A full-adder has a Cin = 0. What are the sum and the carry (Cout) when A = 1 and B = 1?
A.	= 0, cout = 0
B.	= 0, cout = 1
C.	= 1, cout = 0
D.	= 1, cout = 1
Answer» B. = 0, cout = 1

385.	When adding an even parity bit to the code 110010, the result is .
A.	1110010
B.	110010
C.	1111001
D.	1101
Answer» A. 1110010

386.	Which of the following combinations of logic gates can decode binary 1101?
A.	one 4-input and gate
B.	one 4-input and gate, one or gate
C.	one 4-input nand gate, one inverter
D.	one 4- input and gate, one inverter
Answer» D. one 4- input and gate, one inverter

387.	What is the indication of a short to ground in the output of a driving gate?
A.	only the output of the defective gate is affected.
B.	there is a signal loss to all load gates.
C.	the node may be stuck in either the high or the low state.
D.	the affected node will be stuck in the high state.
Answer» B. there is a signal loss to all load gates.

388.	How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have?
A.	3
B.	4
C.	5
D.	6
Answer» B. 4

389.	A half-adder does not have .
A.	carry in
B.	carry out
C.	two inputs
D.	all of the above
Answer» A. carry in

390.	A circuit that can convert one of ten numerical keys pressed on a keyboard to BCD is a .
A.	priority encoder
B.	decoder
C.	multiplexer
D.	demultiple xer
Answer» A. priority encoder

391.	The prefix on IC’s indicates a broader operating temperature range, and the devices are generally used by the military.
A.	54
B.	2n
C.	74
D.	ttl
Answer» A. 54

392.	When an open occurs on the input of a TTL device, the output will .
A.	go low, because there is no current in an open circuit
B.	react as if the open input were a high
C.	go high, since full voltage appears across an open
D.	still be good, if only the good inputs are used
Answer» B. react as if the open input were a high

393.	The largest truth table that can be implemented directly with an 8-line- to-1-line MUX has .
A.	3 rows
B.	4 rows
C.	8 rows
D.	16 rows
Answer» C. 8 rows

394.	Parity generation and checking is used to detect .
A.	which of two numbers is greater
B.	errors in binary data transmission
C.	errors in arithmetic in computers
D.	when a binary counter counts incorrectly
Answer» B. errors in binary data transmission

395.	Except for , STD_LOGIC may have the following values.
A.	\z\
B.	\u\
C.	\?\
D.	\l\
Answer» C. \?\

396.	A gate that could be used to compare two logic levels and provide a HIGH output if they are equal is a(n) .
A.	xor gate
B.	xnor gate
C.	nand gate
D.	nor gate
Answer» B. xnor gate

397.	VHDL is very strict in the way it allows us to assign and compare such as signals, variables, constants, and literals.
A.	objects
B.	logic_vect ors
C.	designs
D.	arrays
Answer» A. objects

398.	The AND-OR-INVERT gates are designed to simplify implementation of .
A.	pos logic
B.	demorgan\s theorem
C.	nand logic
D.	sop logic
Answer» B. demorgan\s theorem

399.	The output of a gate has an internal short; a current tracer will .
A.	identify the defective gate
B.	show whether the gate is shorted to v cc or ground
C.	probably not be able to locate the problem
D.	be able to identify the defective load node
Answer» A. identify the defective gate

401.	The 7447A is a BCD-to-7-segment decoder with ripple blanking input and output functions. The purpose of these lines is to .
A.	turn off the display for any nonsignificant digit
B.	turn off the display for any zero
C.	turn off the display for leading or trailing zeros
D.	test the display to assure all segments are operationa l
Answer» A. turn off the display for any nonsignificant digit

402.	One reason for using the sum-of-products form is that it can be implemented using all gates without much difficulty.
A.	nor
B.	nand
C.	and
D.	door
Answer» B. nand

403.	When an open occurs on the input of a CMOS gate, the output will .
A.	go low, because there is no current in an open circuit
B.	react as if the open input were a high
C.	go high, since full voltage appears across an open
D.	be unpredicta ble; it may go high or low
Answer» D. be unpredicta ble; it may go high or low

404.	To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2’s complement system, the minuend is .
A.	complemented only if it is positive
B.	complemente d only if it is negative
C.	always complemente d
D.	never compleme nted
Answer» D. never compleme nted

405.	In an odd-parity system, the data that will produce a parity bit = 1 is .
A.	data = 1010011
B.	data = 1111000
C.	data = 1100000
D.	all of the above
Answer» D. all of the above

406.	The addition of two signed numbers in the 2’s complement system can cause overflow. For overflow to occur both numbers must .
A.	be positive
B.	be negative
C.	have the same sign
D.	have opposite signs
Answer» C. have the same sign

407.	A Karnaugh map will .
A.	eliminate the need for tedious boolean simplifications
B.	allow any circuit to be implemented with just and and or gates
C.	produce the simplest sum-of- products expression
D.	give an overall picture of how the signals flow through the logic circuit
Answer» A. eliminate the need for tedious boolean simplifications

408.	An 8-bit binary number is input to an odd parity generator. The parity bit will equal 1 only if .
A.	the number is odd
B.	the number of 1s in the number is odd
C.	the number is even
D.	the number of 1s in the number is even
Answer» D. the number of 1s in the number is even

409.	Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected .
A.	to the outputs from the least significant 4- bit comparator
B.	to the cascading inputs of the least significant 4- bit comparator
C.	a = b to a logic high, a < b and a > b to a logic low
D.	ground
Answer» A. to the outputs from the least significant 4- bit comparator

410.	When Karnaugh mapping, we must be sure to use the number of loops.
A.	maximum
B.	minimum
C.	median
D.	karnaugh
Answer» B. minimum

411.	The final output of a POS circuit is generated by .
A.	an and
B.	an or
C.	a nor
D.	a nand
Answer» A. an and

412.	After each circuit in a subsection of a VHDL program has been , they can be combined and the subsection can be tested.
A.	designed
B.	tested
C.	engineered
D.	produced
Answer» B. tested

413.	The series of IC’s are pin, function, and voltage-level compatible with the 74 series IC’s.
A.	als
B.	cmos
C.	hct
D.	2n
Answer» C. hct

414.	The circuit produces a HIGH output whenever the two inputs are equal.
A.	exclusive-and
B.	exclusive- nand
C.	exclusive- nor
D.	exclusive- or
Answer» C. exclusive- nor

415.	A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be .
A.	1100
B.	10101
C.	11000
D.	11
Answer» C. 11000

416.	The statement evaluates the variable status.
A.	if/then
B.	if/then/el se
C.	case
D.	elsif
Answer» A. if/then

417.	In VHDL, data can be each of the following types except .
A.	bit
B.	bit_vector
C.	std_logic
D.	std_vect or
Answer» D. std_vect or

418.	When grouping cells within a K-map, the cells must be combined in groups of .
A.	2\s
B.	1, 2, 4, 8, etc.
C.	4\s
D.	3\s
Answer» B. 1, 2, 4, 8, etc.

419.	The circuit produces a HIGH output whenever the two inputs are unequal.
A.	exclusive-and
B.	exclusive- nor
C.	exclusive-or
D.	inexclusive -or
Answer» C. exclusive-or

420.	Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in terms in the K-map and can be treated as either or , in order to the resulting term.
A.	don\t care, 1\s, 0\s, simplify
B.	spurious, and\s, or\s, eliminate
C.	duplicate, 1\s, 0\s, verify
D.	spurious, 1\s, 0\s, simplify
Answer» A. don\t care, 1\s, 0\s, simplify

421.	A good rule of thumb for determining the pin numbers of dual-in-line package IC chips would be to place the notch to your right and pin #1 will always be in the lower right corner.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

422.	The carry output of each adder in a ripple adder provides an additional sum output bit.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

423.	Truth tables are great for listing all possible combinations of independent variables.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

424.	A square in the top row of a K-map is considered to be adjacent to its corresponding square in the bottom row.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

426.	The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active- low outputs is 1110. As a result, output line 7 is driven LOW.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

427.	When decisions demand two possible actions, the IF/THEN/ELSE control structure is used.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

428.	TTL stands for transistor-technology-logic.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

429.	The 54 prefix on ICs indicates a broader operating temperature range, generally intended for military use.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

430.	This is an example of a POS expression:
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

431.	The abbreviation for an exclusive-OR gate is XOR.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

432.	In an even-parity system, the parity bit is adjusted to make an even number of one bits.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

433.	In an even-parity system, the following data will produce a parity bit = 1. data = 1010011
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

434.	The following combination is correct for an ODD parity data transmission system: data = 011011100 and parity = 0
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

435.	The XOR gate will produce a HIGH output if only one but not both of the inputs is HIGH.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

436.	When decisions demand one of many possible actions, the ELSIF control structure is used.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

437.	The K-map provides a “graphical” approach to simplifying sum-of- products expressions.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

438.	Even parity is the condition of having an even number of 1s in every group of bits.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

439.	The look-ahead carry method suffers from propagation delays.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

440.	A pull-up resistor is a resistor used to keep a given point in a circuit HIGH when in the active state.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

441.	A data selector is also called a demultiplexer.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

442.	A digital circuit that converts coded information into a familiar or non- coded form is known as an encoder.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

443.	An exclusive-OR gate will invert a signal on one input if the other is always HIGH.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

444.	The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

445.	The CASE control structure is used when an expression has a list of possible values.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

446.	An encoder in which the highest and lowest value input digits are encoded simultaneously is known as a priority encoder.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

447.	Three select lines are required to address four data input lines.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

448.	Single looping in groups of three is a common K-map simplification technique.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» B. false

449.	In true sum-of-products expressions, the inversion signs cannot cover more than single variables in a term.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» A. true

451.	Which of the following is not a form of multivibrator?
A.	astable.
B.	monostable.
C.	tristable.
D.	bistable.
Answer» C. tristable.

452.	A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously?
A.	the q output toggles to the other state.
B.	the q output is set to 1.
C.	the q output is reset to 0.
D.	the q output remains unchanged .
Answer» A. the q output toggles to the other state.

453.	A master/slave bistable is formed using two bistable connected in series.
A.	true
B.	false
Answer» A. true

454.	An astable has two metastable states and produces the function of a digital oscillator
A.	true
B.	false
Answer» A. true

455.	In synchronous counters the clock input of each of the bistables are connected together so that each changes state at the same time.
A.	true
B.	false
Answer» A. true

456.	1: When the maximum clock rate is quoted for a logic family, then it applies to a
A.	shift register
B.	flip-flop
C.	counter
D.	multiplexe r
Answer» B. flip-flop

457.	2: The number of flip-flops required in a modulo N counter is
A.	log2 (n) + 1
B.	log2(n-1)
C.	log2 (n)
D.	n log2 (n)
Answer» C. log2 (n)

458.	3: Flip-flop outputs are always
A.	complimentary
B.	the same
C.	independent of each other
D.	same as previous input
Answer» A. complimentary

459.	4: How many gates (minimum) are needed for a 3-bit up-counter using standard binary and using T lip-lops ? Assume unlimited fan-in.
A.	6
B.	3
C.	2
D.	1
Answer» C. 2

460.	5: The clear data and present input of the JK lip-lop are known as
A.	synchronous inputs
B.	directed inputs
C.	either (a) or (b)
D.	none of thes
Answer» C. either (a) or (b)

461.	A mod-2 counter followed by a mod-5 counter is
A.	same as a mode-5 counter followed by a mod- 2 counter
B.	a decade counter
C.	a mod-7 counter
D.	ripple carry counter
Answer» A. same as a mode-5 counter followed by a mod- 2 counter

462.	What is the maximum counting speed of a 4-bit binary counter which is composed of flip-flops with a propagation delay of 25 ns ?
A.	1 mhz
B.	10 mhz
C.	100 mhz
D.	8 mhz
Answer» B. 10 mhz

463.	8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now
A.	change its state at each clock pulse
B.	go to state 1 and stay there
C.	go to state 0 and stay there
D.	retain its previous state
Answer» D. retain its previous state

464.	9: Consider an RS lip-lops with both inputs set to 0. If a momentary ‘1’ is applied at the input S,then the output
A.	q will flip from 0 to 1 and then back to 0
B.	q will flip from 0 to 1 and then back to 0
C.	q will flip from 1 to 0
D.	q will flip from 0 to 1
Answer» D. q will flip from 0 to 1

465.	The output of a sequential circuit depends on
A.	present inputs only
B.	past outputs only
C.	both present and past inputs
D.	present outputs only
Answer» C. both present and past inputs

466.	The ring counter is analogous to
A.	toggle switch
B.	latch
C.	stepping switch
D.	j-k flip- flop
Answer» C. stepping switch

467.	12: In a digital counter circuit feedback loop is introduced to
A.	improve distortion
B.	improve stability
C.	reduce the number of input pulses to reset the counter
D.	asynchron ous input and output pulses
Answer» C. reduce the number of input pulses to reset the counter

468.	A J-K lip-lop has its J-input connected to logic level 1 and its input to the Q output pulse is fed to its clock input the flip-flop will now
A.	change its state at each clock pulse
B.	go to state 1 and stay there
C.	go to state 0 and stay there
D.	retain its present state
Answer» A. change its state at each clock pulse

469.	Which of the following conditions must be met to avoid race around problem ?
A.	Δ t < tp < t
B.	t > Δt > tp
C.	2 tp < Δt < t
D.	none of these
Answer» B. t > Δt > tp

470.	Match List I with List II and select the correct answer form the codes given below the list List I A. A shift register can be B. A multiplexer C. A decoder can List II 1.for parallel to serial conversion 2.to generate memory can be used chip select 3.for parallel to serial conversion CODES: A B C
A.	3 1 2
B.	2 3 1
C.	1 3 2
D.	1 2 3
Answer» C. 1 3 2

471.	With the use of an electronic counter six capsules are to be filled in bottles automatically. In such a counter what will be the number of flip- flops required ?
A.	3
B.	12
C.	6
D.	8
Answer» C. 6

472.	A pulse train can be delayed by a finite number of clock periods using
A.	a serial-in serial-out shift register
B.	a serial-in parallel-out shift register
C.	both (a) and (b)
D.	a parallel- in parallel- out shift register
Answer» D. a parallel- in parallel- out shift register

473.	How many illegitimate states has synchronous mod-6 counter ?
A.	3
B.	2
C.	1
D.	6
Answer» A. 3

474.	A 2 bit binary multiplier can be implemented using
A.	2 input ands only
B.	2 input xors and 4 input and gates only
C.	2 input nors and one xnor gate
D.	nor gates and shift registers
Answer» B. 2 input xors and 4 input and gates only

476.	The dynamic hazard problem occurs in
A.	combinational circuit alone
B.	sequential circuit only
C.	both (a) and (b)
D.	none of these
Answer» C. both (a) and (b)

477.	A n-stage ripple counter will count up to
A.	2n
B.	2n-1
C.	n
D.	2n-1
Answer» A. 2n

478.	The clock signals are used in sequential logic circuits to
A.	tell the time of the day
B.	tell how much time has elapsed since the system was turned on
C.	carry parllel data signals
D.	synchroniz e events in various parts of system
Answer» D. synchroniz e events in various parts of system

479.	74L5138 chip functions as
A.	decoder/demu ltiplexer
B.	encoder
C.	multiplexer
D.	demultiple xer
Answer» A. decoder/demu ltiplexer

480.	A sequential circuit outputs a ONE when an even number (> 0) of one’s are input; otherwise the output is ZERO. The minimum number of states required is
A.	0
B.	1
C.	2
D.	none of these
Answer» C. 2

481.	A shift register can be used for
A.	digital delay line
B.	serial to parallel conversion
C.	parallel to serial conversion
D.	all of these
Answer» D. all of these

482.	Popular application of flip-flop are
A.	transfer register
B.	shift registers
C.	counters
D.	all of these
Answer» D. all of these

483.	For which of the following flip-flops, the output is clearly defined for all combinations of two inputs ?
A.	q type flip-flop
B.	r-s flip-lop
C.	j-k flip-lop
D.	d flip-flop
Answer» C. j-k flip-lop

484.	When a large number of analog signals are to be converted an analog multiplexer is used. In this case most suitable A.D. converter will be
A.	ripple carry counter type
B.	dual stop type
C.	forward counter type
D.	successive approxima tion type
Answer» D. successive approxima tion type

485.	To build a mod-19 counter the number of flip-flops required is
A.	3
B.	5
C.	7
D.	9
Answer» B. 5

486.	The astable multivibrator has
A.	two quasi stable states
B.	two stable states
C.	one stable and one quasi-stable state
D.	none of these
Answer» A. two quasi stable states

487.	How many bits are required to encode all twenty six letters, ten symbols, and ten numerals ?
A.	5
B.	6
C.	10
D.	48
Answer» B. 6

488.	The functional difference between S-R flip-flop and J-K flip-flop is that J- K flip-flop
A.	is faster than s- r flip-flop
B.	has a feed- back path
C.	accepts both inputs 1
D.	both (a) and (b)
Answer» C. accepts both inputs 1

489.	In a positive edge triggered JK flip-flop, a low J and low K produces
A.	no change
B.	low state
C.	high state
D.	none of thes
Answer» A. no change

490.	When an inverter is placed between both inputs of an SR flip-flop, then resulting flip-lop is
A.	jk flip-flop
B.	d flip-flop
C.	sr flip-flop
D.	master slave jk flip-flop
Answer» B. d flip-flop

491.	A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the ‘toggle’ mode. The frequency of the signal at the output will be
A.	1 mhz
B.	2 mhz
C.	6 mhz
D.	8 mhz
Answer» D. 8 mhz

492.	The master slave JK lip-flop is effectively a combination of
A.	a sr flip-flop and a t flip- flop
B.	an sr flip- lfop and a d flip-flop
C.	a t flip-flop and a d flip- flop
D.	two d flip- flops
Answer» A. a sr flip-flop and a t flip- flop

493.	It is difficult to design asynhronous sequential circuit because
A.	external clock is to be provided
B.	it is more complex
C.	both (a) and (b)
D.	generally they involve stability problem
Answer» D. generally they involve stability problem

494.	A stable multivibrator is used as
A.	comparator circuit
B.	demultiplexe r
C.	frequency to voltage converter
D.	voltage to frequency converter
Answer» A. comparator circuit

495.	How many flip-flop are needed to divide the input frequency by 64 ?
A.	2
B.	5
C.	6
D.	8
Answer» C. 6

496.	41: In a ripple counter using edge triggered JK flfp-flops, the pulse input is applied to the
A.	clock input of all flip-flops
B.	clock input of one flip- flops
C.	j and k inputs of all flip-flops
D.	j and k inputs of one flip- flop
Answer» C. j and k inputs of all flip-flops

497.	The number of clock pulses needed to shift one byte of data from input to the output of a 4-bit shift register is
A.	10
B.	12
C.	16
D.	32
Answer» C. 16

498.	The main difference between JK and RS flip-flop is that
A.	jk flip flop needs a clock pulse
B.	there is a feedback in jk lip-lop
C.	jk flip-flop accepts both inputs as 1
D.	jk flip-flop is acronym of junction cathode multivibra tor
Answer» C. jk flip-flop accepts both inputs as 1

499.	Which of the following unit will choose to transform decimal number to binary code ?
A.	encoder
B.	decoder
C.	multiplexer
D.	counter
Answer» A. encoder

501.	Which of the following flip-flop is free from race-around problem ?
A.	q flip-flop
B.	t flip-flop
C.	sr flip-flop
D.	master- slave jk flip-flop
Answer» D. master- slave jk flip-flop

502.	If the input J is connected through K input of J-K, then flip-flop will behave as a
A.	d type flip-flop
B.	t type flip- flop
C.	s-r flip-flop
D.	master slave jk flip-flop
Answer» A. d type flip-flop

503.	If a clock with time period ‘T’ is used with n stage shift register, then output of final stage will be delayed by
A.	nt sec
B.	(n-1)t sec
C.	n/t sec
D.	(2n+1)t sec
Answer» B. (n-1)t sec

504.	Register is a
A.	set of capacitor used to register input instructions in a digital computer
B.	set to paper tapes and cards put in a file
C.	temporary storage unit within the cpu having dedicated or general purpose use
D.	part of the main memory
Answer» C. temporary storage unit within the cpu having dedicated or general purpose use

505.	The number of flip-flops required in a decade counter is
A.	3
B.	4
C.	8
D.	10
Answer» B. 4

506.	If in a shift resistor Q0 is fed back to input the resulting counter is
A.	twisted ring with n : 1 scale
B.	ring counter with n : 1 scale
C.	twisted ring with 2n : 1 scale
D.	ring counter with 2 n : 1 scale
Answer» C. twisted ring with 2n : 1 scale

507.	A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift the value completely out of the register.
A.	1
B.	2
C.	4
D.	8
Answer» D. 8

508.	In a sequential circuit the next state is determined by and
A.	state variable, current state
B.	current state, flip- flop output
C.	current state and external input
D.	input and clock signal applied
Answer» D. input and clock signal applied

509.	The divide-by-60 counter in digital clock is implemented by using two cascading counters:
A.	mod-6, mod-10
B.	mod-50, mod-10
C.	mod-10, mod-50
D.	mod-50, mod-6
Answer» A. mod-6, mod-10

510.	In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
A.	true
B.	false
Answer» A. true

511.	The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop.
A.	set-up time
B.	hold time
C.	pulse interval time
D.	pulse stability time (pst)
Answer» B. hold time

512.	74HC163 has two enable input pins which are and
A.	enp, ent
B.	eni, enc
C.	enp, enc
D.	ent, eni
Answer» A. enp, ent

513.	to change in one input variable
A.	clock skew
B.	condition
C.	hold delay
D.	wait
Answer» B. condition

514.	The input overrides the input
A.	asynchronous , synchronous
B.	synchronous, asynchronou s
C.	preset input (pre), clear input (clr)
D.	clear input (clr), preset input (pre)
Answer» A. asynchronous , synchronous

515.	A decade counter is .
A.	mod-3 counter
B.	mod-5 counter
C.	mod-8 counter
D.	mod-10 counter
Answer» D. mod-10 counter

516.	In asynchronous transmission when the transmission line is idle,
A.	it is set to logic low
B.	it is set to logic high
C.	remains in previous state
D.	state of transmissi on line is not used to start transmissi on
Answer» B. it is set to logic high

517.	A Nibble consists of bits
A.	2
B.	4
C.	8
D.	16
Answer» B. 4

518.	The output of this circuit is always .
A.	1
B.	0
C.	a
D.	abar
Answer» C. a

519.	Excess-8 code assigns to “-8”
A.	1110
B.	1100
C.	1000
D.	0
Answer» D. 0

520.	The voltage gain of the Inverting Amplifier is given by the relation
A.	vout / vin = – rf / ri
B.	vout / rf = – vin / ri
C.	rf / vin = – ri / vout
D.	rf / vin = ri / vout
Answer» A. vout / vin = – rf / ri

521.	LUT is acronym for
A.	look up table
B.	local user terminal
C.	least upper time period
D.	none of given options
Answer» A. look up table

522.	The three fundamental gates are
A.	and, nand, xor
B.	or, and, nand
C.	not, nor, xor
D.	not, or, and
Answer» D. not, or, and

523.	Stack is an acronym for
A.	fifo memory
B.	lifo memory
C.	flash memory
D.	bust flash memory
Answer» B. lifo memory

524.	is one of the examples of synchronous inputs.
A.	j-k input
B.	en input
C.	preset input (pre)
D.	clear input (clr)
Answer» A. j-k input

526.	Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be
A.	0
B.	1101
C.	1011
D.	1111
Answer» C. 1011

527.	In a state diagram, the transition from a current state to the next state is determined by
A.	current state and the inputs
B.	current state and outputs
C.	previous state and inputs
D.	previous state and outputs
Answer» A. current state and the inputs

528.	is used to simplify the circuit that determines the next state.
A.	state diagram
B.	next state table
C.	state reduction
D.	state assignmen t
Answer» D. state assignmen t

529.	Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
A.	1100
B.	11
C.	0
D.	1111
Answer» C. 0

530.	The diagram given below represents
A.	demorgans law
B.	associative law
C.	product of sum form
D.	sum of product form
Answer» D. sum of product form

531.	The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop
A.	doesn’t have an invalid state
B.	sets to clear when both j = 0 and k = 0
C.	it does not show transition on change in pulse
D.	it does not accept asynchron ous inputs
Answer» A. doesn’t have an invalid state

532.	A multiplexer with a register circuit converts
A.	serial data to parallel
B.	parallel data to serial
C.	serial data to serial
D.	parallel data to parallel
Answer» B. parallel data to serial

533.	A GAL is essentially a .
A.	non- reprogrammab le pal
B.	pal that is programmed only by the manufacture r
C.	very large pal
D.	reprogra mmable pal
Answer» D. reprogra mmable pal

534.	in , all the columns in the same row are either read or written.
A.	sequential access
B.	mos access
C.	fast mode page access
D.	none of given options
Answer» C. fast mode page access

535.	How many flip-flops are required to produce a divide-by-32 device?
A.	2
B.	5
C.	6
D.	4
Answer» B. 5

536.	A reduced state table has 18 rows. The minimum number of flip flops needed to implement the sequential machine is
A.	18
B.	9
C.	5
D.	4
Answer» C. 5

537.	Advantage of synchronous sequential circuits over asynchronous ones is
A.	faster operation
B.	ease of avoiding problems due to hazard
C.	lower hardware requirement
D.	better noise immunity
Answer» A. faster operation

538.	The characteristic equation of a JK flip flop is
A.	qn+1=j.qn+k.q n
B.	qn+1=j.q’n+ k’.qn
C.	qn+1=qnj.k
D.	qn+1=(j+k )qn
Answer» B. qn+1=j.q’n+ k’.qn

539.	WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO ——-
A.	the flop- flop is triggered
B.	q=0 and q‟=1
C.	q=1 and q‟=0
D.	the output of flip- flop remains unchang ed
Answer» D. the output of flip- flop remains unchang ed

540.	In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register.
A.	moore machine
B.	meally machine
C.	johnson counter
D.	ring counter
Answer» D. ring counter

541.	5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES
A.	7
B.	10
C.	32
D.	25
Answer» B. 10

542.	A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift the value completely out of the register.
A.	1
B.	2
C.	4
D.	8
Answer» D. 8

543.	AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES?
A.	2
B.	4
C.	6
D.	8
Answer» D. 8

544.	The alternate solution for a multiplexer and a register circuit is
A.	parallel in / serial out shift register
B.	serial in / parallel out shift register
C.	parallel in / parallel out shift register
D.	serial in / serial out shift register
Answer» A. parallel in / serial out shift register

545.	A multiplexer with a register circuit converts
A.	serial data to parallel
B.	parallel data to serial
C.	serial data to serial
D.	parallel data to parallel
Answer» B. parallel data to serial

546.	A synchronous decade counter will have flip-flops
A.	3
B.	4
C.	7
D.	10
Answer» B. 4

547.	In outputs depend only on the current state.
A.	mealy machine
B.	moore machine
C.	state reduction table
D.	state assignmen t table
Answer» B. moore machine

548.	Given the state diagram of an up/down counter, we can find
A.	the next state of a given present state
B.	the previous state of a given present state
C.	both the next and previous states of a given state
D.	the state diagram shows only the inputs/out puts of a given states
Answer» A. the next state of a given present state

549.	THE HOURS COUNTER IS IMPLEMENTED USING
A.	only a single mod- 12 counter is required
B.	mod-10 and mod-6 counters
C.	mod-10 and mod-2 counters
D.	a single decade counter and a flip-flop
Answer» D. a single decade counter and a flip-flop

551.	THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A
A.	gated flip- flops
B.	pulse triggered flip-flops
C.	positive- edge triggered flip-flops
D.	negative -edge triggere d flip- flops
Answer» D. negative -edge triggere d flip- flops

552.	A positive edge-triggered flip-flop changes its state when
A.	low-to-high transition of clock
B.	high-to-low transition of clock
C.	enable input (en) is set
D.	preset input (pre) is set
Answer» A. low-to-high transition of clock

553.	Flip flops are also called
A.	bi-stable dualvibrators
B.	bi-stable transformer
C.	bi-stable multivibrator s
D.	bi-stable singlevibra tors
Answer» C. bi-stable multivibrator s

554.	A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER.
A.	true
B.	false
Answer» A. true

555.	THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT GATE
A.	and
B.	or
C.	nand
D.	xor
Answer» B. or

556.	A particular half adder has
A.	2 inputs and 1 output
B.	2 inputs and 2 output
C.	3 inputs and 1 output
D.	3 inputs and 2 output
Answer» B. 2 inputs and 2 output

557.	A full-adder has a Cin = 0. What are the sum (<PRIVATE “TYPE=PICT;ALT=sigma”> ) and the carry (Cout) when A = 1 and B = 1?
A.	= 0, cout = 0
B.	= 0, cout = 1
C.	= 1, cout = 0
D.	= 1, cout = 1
Answer» B. = 0, cout = 1

558.	The sequence of states that are implemented by a n-bit Johnson counter is
A.	n+2 (n plus 2)
B.	2n (n multiplied by 2)
C.	2n (2 raise to power n)
D.	n2 (n raise to power 2)
Answer» B. 2n (n multiplied by 2)

559.	A GAL is essentially a .
A.	non- reprogrammab le pal
B.	pal that is programmed only by the manufacture r
C.	very large pal
D.	reprogra mmable pal
Answer» D. reprogra mmable pal

560.	The alternate solution for a demultiplexer-register combination circuit is
A.	parallel in / serial out shift register
B.	serial in / parallel out shift register
C.	parallel in / parallel out shift register
D.	serial in / serial out shift register
Answer» B. serial in / parallel out shift register

561.	A transparent mode means
A.	the changes in the data at the inputs of the latch are seen at the output
B.	the changes in the data at the inputs of the latch are not seen at the output
C.	propagation delay is zero (output is immediately changed when clock signal is applied)
D.	input hold time is zero (no need to maintain input after clock transition)
Answer» A. the changes in the data at the inputs of the latch are seen at the output

562.	occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
A.	race condition
B.	clock skew
C.	ripple effect
D.	none of given options
Answer» B. clock skew

563.	is one of the examples of asynchronous inputs.
A.	j-k input
B.	s-r input
C.	d input
D.	clear input (clr)
Answer» D. clear input (clr)

564.	Bi-stable devices remain in either of their states unless the inputs force the device to switch its state
A.	ten
B.	eight
C.	three
D.	two
Answer» D. two

565.	RCO Stands for
A.	reconfiguratio n counter output
B.	reconfigurati on clock output
C.	ripple counter output
D.	ripple clock output
Answer» D. ripple clock output

566.	A positive edge-triggered flip-flop changes its state when
A.	low-to-high transition of clock
B.	high-to-low transition of clock
C.	enable input (en) is set
D.	preset input (pre) is set
Answer» A. low-to-high transition of clock

567.	The low to high or high to low transition of the clock is considered to be a(n)
A.	state
B.	edge
C.	trigger
D.	one-shot
Answer» B. edge

568.	In asynchronous digital systems all the circuits change their state with respect to a common clock
A.	true
B.	false
Answer» B. false

569.	If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)
A.	and
B.	or
C.	not
D.	xor
Answer» C. not

570.	If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop
A.	0
B.	1
C.	invalid
D.	input is invalid
Answer» B. 1

571.	3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
A.	true
B.	false
Answer» A. true

572.	The Encoder is used as a keypad encoder.
A.	2-to-8 encoder
B.	4-to-16 encoder
C.	bcd-to- decimal
D.	decimal- to-bcd priority
Answer» D. decimal- to-bcd priority

573.	The simplest and most commonly used Decoders are the Decoders
A.	n to 2n
B.	(n-1) to 2n
C.	(n-1) to (2n- 1)
D.	n to 2n-1
Answer» A. n to 2n

574.	A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value.
A.	true
B.	false
Answer» A. true

576.	Q2 :=Q1 OR X OR Q3 The above ABEL expression will be
A.	q2:= q1 $ x $ q3
B.	q2:= q1 # x # q3
C.	q2:= q1 & x & q3
D.	q2:= q1 ! x ! q3
Answer» B. q2:= q1 # x # q3

577.	Above is the circuit diagram of
A.	asynchronous up-counter
B.	asynchronou s down- counter
C.	synchronous up-counter
D.	synchrono us down- counter
Answer» A. asynchronous up-counter

578.	The high density FLASH memory cell is implemented using
A.	1 floating-gate mos transistor
B.	2 floating- gate mos transistors
C.	4 floating- gate mos transistors
D.	6 floating- gate mos transistors
Answer» A. 1 floating-gate mos transistor

579.	A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing .
A.	1110
B.	111
C.	1000
D.	1001
Answer» D. 1001

580.	At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?
A.	2
B.	4
C.	6
D.	8
Answer» D. 8

581.	A multiplexer with a register circuit converts
A.	serial data to parallel
B.	parallel data to serial
C.	serial data to serial
D.	parallel data to parallel
Answer» B. parallel data to serial

582.	In outputs depend only on the combination of current state and inputs
A.	mealy machine
B.	moore machine
C.	state reduction table
D.	state assignmen t table
Answer» A. mealy machine

583.	The input overrides the input
A.	asynchronous, synchronous
B.	synchronous, asynchronou s
C.	preset input (pre), clear input (clr)
D.	clear input (clr), preset input (pre)
Answer» A. asynchronous, synchronous

584.	For a gated D-Latch if EN=1 and D=1 then Q(t+1) =
A.	0
B.	1
C.	q(t)
D.	invalid
Answer» B. 1

585.	If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop
A.	0
B.	1
C.	invalid
D.	input is invalid
Answer» C. invalid

586.	The sequence of states that are implemented by a n-bit Johnson counter is
A.	n+2
B.	2n
C.	2 raise to power n
D.	n raise to power 2
Answer» B. 2n

587.	The alternate solution for a multiplexer and a register circuit is
A.	parallel in / serial out shift register
B.	serial in / parallel out shift register
C.	parallel in / parallel out shift register
D.	serial in / serial out shift register
Answer» A. parallel in / serial out shift register

588.	THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A
A.	gated flip- flops
B.	pulse triggered flip-flops
C.	positive- edge triggered flip-flops
D.	negative -edge triggere d flip- flops
Answer» D. negative -edge triggere d flip- flops

589.	Flip flops are also called
A.	bi-stable dualvibrators
B.	bi-stable transformer
C.	bi-stable multivibrator s
D.	bi-stable singlevibra tors
Answer» C. bi-stable multivibrator s

590.	A transparent mode means
A.	the changes in the data at the inputs of the latch are seen at the output
B.	the changes in the data at the inputs of the latch are not seen at the output
C.	propagation delay is zero (output is immediately changed when clock signal is applied)
D.	input hold time is zero (no need to maintain input after clock transition)
Answer» A. the changes in the data at the inputs of the latch are seen at the output

591.	Given the state diagram of an up/down counter, we can find
A.	the next state of a given present state
B.	the previous state of a given present state
C.	both the next and previous states of a given state
D.	the state diagram shows only the inputs/out puts of a given states
Answer» A. the next state of a given present state

592.	In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register.
A.	moore machine
B.	meally machine
C.	johnson counter
D.	ring counter
Answer» D. ring counter

593.	status.
A.	3
B.	7
C.	8
D.	15
Answer» C. 8

594.	We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
A.	using s-r flop- flop
B.	d-flipflop
C.	j-k flip-flop
D.	t-flip-flop
Answer» C. j-k flip-flop

595.	If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop
A.	0
B.	1
C.	invalid
D.	input is invalid
Answer» C. invalid

596.	WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO
A.	the flop- flop is triggered
B.	q=0 and q‟=1
C.	q=1 and q’=0
D.	the output of flip- flop remains unchang ed
Answer» C. q=1 and q’=0

597.	If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be
A.	set
B.	reset
C.	invalid
D.	clear
Answer» A. set

598.	For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH.
A.	toggle
B.	set
C.	reset
D.	not change
Answer» A. toggle

599.	What is the difference between a D latch and a D flip-flop?
A.	the d latch has a clock input.
B.	the d flip- flop has an enable input.
C.	the d latch is used for faster operation.
D.	the d flip- flop has a clock input.
Answer» D. the d flip- flop has a clock input.

601.	Convert the binary number 10110 to Gray code:
A.	11101
B.	11001
C.	10101
D.	11100
Answer» A. 11101

602.	The Gray code for decimal number 6 is equivalent to
A.	1100
B.	1001
C.	101
D.	110
Answer» C. 101

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